Design of Pseudo Random Binary Sequence Generator using VHDL

Pseudo Random binary Sequence Generator technique are used for various cryptographic applications and for designing encoder, decoder in different communication channel . The implementation of PRBS generator is based on the linear feedback shift register (LFSR).The total number of random state generated by the LFSR depends on the feedback polynomial. It is nothing but a simple counter so it can count maximum of 2n -1 cycle by using maximum feedback polynomial. In this paper, the entire design of the PRBS generator is implemented using VHDL

Design of 8 and 16 Bit LFSR with Maximum Length Feedback Polynomial & Its pipelined Structure Using Verilog HDL

This paper is mainly concerned with the design of random sequences using Linear Feedback Shift Register (LFSR). This pseudo sequences is mainly used for various communication purposes. The other application such as banking, cryptographic, encoder & decoder. For hardware prototype FPGA is used because of its flexibility to reconfigure design many times. LFSR is a shift register whose output random state depends upon feedback polynomial. But by using pipelined architecture we can reduce the timing of random pattern generated at output by reducing the critical path. It can count maximum 2n-1 states and produce pseudo-random number at the output. Finally, comparing the simple and pipelined architecture of 8 & 16-bit LFSR

Segmented Leap-Ahead LFSR Architecture for Uniform Random Number Generator

Random numbers are widely used in various applications. In the majority of cases, a pseudo-random number generator is used since true random number generators are slow and they are barely suitable for the hardware implementation. In this paper, we present new architecture of URNG (uniform random number generator) employing Leap-Ahead LFSR architecture for hardware implementation. In particular, the proposed URNG consists of two more segmented Leap-Ahead LFSRs to overcome the drawback of the conventional URNG employing Leap-Ahead architecture, that is, the sharp decrease of a maximum period of the generated random numbers. Thus, the proposed URNG with segmented LFSR architecture can generate multiple bits random number in a cycle without the frequent diminishing of maximum period of the generated random numbers. We prove the efficiency of the proposed segmented LFSR-architecture through the mathematical analysis. The simulation results show that the proposed URNG employing segmented Leap-Ahead LFSR architecture can be increased 2.5 times of the maximum period of generated random numbers compared to the URNG using the conventional Leap-Ahead architecture