15,904 research outputs found

    Controlled open-cell two-dimensional liquid foam generation for micro- and nanoscale patterning of materials

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    Liquid foam consists of liquid film networks. The films can be thinned to the nanoscale via evaporation and have potential in bottom-up material structuring applications. However, their use has been limited due to their dynamic fluidity, complex topological changes, and physical characteristics of the closed system. Here, we present a simple and versatile microfluidic approach for controlling two-dimensional liquid foam, designing not only evaporative microholes for directed drainage to generate desired film networks without topological changes for the first time, but also microposts to pin the generated films at set positions. Patterning materials in liquid is achievable using the thin films as nanoscale molds, which has additional potential through repeatable patterning on a substrate and combination with a lithographic technique. By enabling direct-writable multi-integrated patterning of various heterogeneous materials in two-dimensional or three-dimensional networked nanostructures, this technique provides novel means of nanofabrication superior to both lithographic and bottom-up state-of-the-art techniques

    Methodology for standard cell compliance and detailed placement for triple patterning lithography

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    As the feature size of semiconductor process further scales to sub-16nm technology node, triple patterning lithography (TPL) has been regarded one of the most promising lithography candidates. M1 and contact layers, which are usually deployed within standard cells, are most critical and complex parts for modern digital designs. Traditional design flow that ignores TPL in early stages may limit the potential to resolve all the TPL conflicts. In this paper, we propose a coherent framework, including standard cell compliance and detailed placement to enable TPL friendly design. Considering TPL constraints during early design stages, such as standard cell compliance, improves the layout decomposability. With the pre-coloring solutions of standard cells, we present a TPL aware detailed placement, where the layout decomposition and placement can be resolved simultaneously. Our experimental results show that, with negligible impact on critical path delay, our framework can resolve the conflicts much more easily, compared with the traditional physical design flow and followed layout decomposition

    Double Patterning for Memory ICs

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    Design rules for self-assembled block copolymer patterns using tiled templates

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    Directed self-assembly of block copolymers has been used for fabricating various nanoscale patterns, ranging from periodic lines to simple bends. However, assemblies of dense bends, junctions and line segments in a single pattern have not been achieved by using sparse templates, because no systematic template design methods for achieving such complex patterns existed. To direct a complex pattern by using a sparse template, the template needs to encode the key information contained in the final pattern, without being a simple copy of the pattern. Here we develop a set of topographic template tiles consisting of square lattices of posts with a restricted range of geometric features. The block copolymer patterns resulting from all tile arrangements are determined. By combining tiles in different ways, it is possible to predict a relatively simple template that will direct the formation of non-trivial block copolymer patterns, providing a new template design method for a complex block copolymer pattern.Samsung Scholarship FoundationSemiconductor Research CorporationTokyo Electron LimitedTaiwan Semicondcutor Manufacturing CompanyNational Science Foundation (U.S.) (Award DMR1234169

    Scanning evanescent wave lithography for sub-22nm generations

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    Current assumptions for the limits of immersion optical lithography include NA values at 1.35, largely based on the lack of high-index materials. In this research we have been working with ultra-high NA evanescent wave lithography (EWL) where the NA of the projection system is allowed to exceed the corresponding acceptance angle of one or more materials of the system. This approach is made possible by frustrating the total internal reflection (TIR) evanescent field into propagation. With photoresist as the frustrating media, the allowable gap for adequate exposure latitude is in the sub-100 nm range. Through static imaging, we have demonstrated the ability to resolve 26 nm half-pitch features at 193 nm and 1.85 NA using existing materials. Such imaging could lead to the attainment of 13 nm half-pitch through double patterning. In addition, a scanning EWL imaging system was designed, prototyped with a two-stage gap control imaging head including a DC noise canceling carrying air-bearing, and a AC noise canceling piezoelectric transducer with real-time closed-loop feedback from gap detection. Various design aspects of the system including gap detection, feedback actuation, prism design and fabrication, software integration, and scanning scheme have been carefully considered to ensure sub-100 nm scanning. Experiments performed showed successful gap gauging at sub-100 nm scanning height. Scanning EWL results using a two-beam interference imaging approach achieved pattern resolution comparable to static EWL imaging results. With this scanning EWL approach and the imaging head developed, optical lithography becomes extendable to sub-22 nm generations

    Nanogap Device: Fabrication and Applications

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    A nanogap device as a platform for nanoscale electronic devices is presented. Integrated nanostructures on the platform have been used to functionalize the nanogap for biosensor and molecular electronics. Nanogap devices have great potential as a tool for investigating physical phenomena at the nanoscale in nanotechnology. In this dissertation, a laterally self-aligned nanogap device is presented and its feasibility is demonstrated with a nano ZnO dot light emitting diode (LED) and the growth of a metallic sharp tip forming a subnanometer gap suitable for single molecule attachment. For realizing a nanoscale device, a resolution of patterning is critical, and many studies have been performed to overcome this limitation. The creation of a sub nanoscale device is still a challenge. To surmount the challenge, novel processes including double layer etch mask and crystallographic axis alignment have been developed. The processes provide an effective way for making a suspended nanogap device consisting of two self-aligned sharp tips with conventional lithography and 3-D micromachining using anisotropic wet chemical Si etching. As conventional lithography is employed, the nanogap device is fabricated in a wafer scale and the processes assure the productivity and the repeatability. The anisotropic Si etching determines a final size of the nanogap, which is independent of the critical dimension of the lithography used. A nanoscale light emitting device is investigated. A nano ZnO dot is directly integrated on a silicon nanogap device by Zn thermal oxidation followed by Ni and Zn blanket evaporation instead of complex and time consuming processes for integrating nanostructure. The electrical properties of the fabricated LED device are analyzed for its current-voltage characteristic and metal-semiconductor-metal model. Furthermore, the electroluminescence spectrum of the emitted light is measured with a monochromator implemented with a CCD camera to understand the optical properties. The atomically sharp metallic tips are grown by metal ion migration induced by high electric field across a nanogap. To investigate the growth mechanism, in-situ TEM is conducted and the growing is monitored. The grown dendrite nanostructures show less than 1nm curvature of radius. These nanostructures may be compatible for studying the electrical properties of single molecule
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