Low-Noise Amplifier and Noise/Distortion Shaping Beamformer

The emergence of advanced technologies has increased the need for fast and efficient mobile communication that can facilitate transferring large amounts of data and simultaneously serve multiple users. Future wireless systems will rely on millimeter-wave frequencies, enabled by recent silicon hardware advancements. High-frequency millimeter-wave technology and low-noise receiver front ends and amplifiers are key for improved performance and energy efficiency. This thesis proposes two LNA topologies that offer wide input-power-matched bandwidths and low noise figures, eliminating the need for complex matching networks at the LNA input. These topologies use intrinsic feedback through gate-drain networks and/or the resistance of the SOI-transistor back-gate terminal to achieve the real part of the input impedance. The two LNAs are experimentally demonstrated with two 22-nm FDSOI LNAs. One LNA, matched with the assistance of the gate-drain network, exhibits a bandwidth ranging from 7.7-33.3 GHz, which is further improved to 6-38.7 GHz through the application of the back-gate-resistance method. The two LNAs have noise-figure minima of 1.8 and 1.9 dB, maximum gains of 14.7 and 15.6 dB, and maximum IP1dBs of -9.1 and -7.8 dBm while consuming 10 and 7.8 mW of power and occupying 0.04 and 0.03 mm^2 of active areas, respectively. This thesis also presents the first experimental demonstration of noise/distortion (ND) shaping beamformer. The NDs originating in the receiver itself are spatio-temporally shaped away from the beamformer region of support, thereby permitting their suppression by the beamformer. The demonstrator is a 24.3-28.7 GHz, 79.28 mW 4-port receiver for a 4-element antenna array implemented in 22-nm FDSOI CMOS. When shaping was enabled, the concept demonstrator provided average improvements to the NF and IP1dB of 1.6 dB and 2.25 dB, respectively (compared to a reference design), and achieved NF=2.6 dB and IP1dB=-18.7dBm while consuming 19.8 mW/channel

CMOS Data Converters for Closed-Loop mmWave Transmitters

With the increased amount of data consumed in mobile communication systems, new solutions for the infrastructure are needed. Massive multiple input multiple output (MIMO) is seen as a key enabler for providing this increased capacity. With the use of a large number of transmitters, the cost of each transmitter must be low. Closed-loop transmitters, featuring high-speed data converters is a promising option for achieving this reduced unit cost.In this thesis, both digital-to-analog (D/A) and analog-to-digital (A/D) converters suitable for wideband operation in millimeter wave (mmWave) massive MIMO transmitters are demonstrated. A 2 76 bit radio frequency digital-to-analog converter (RF-DAC)-based in-phase quadrature (IQ) modulator is demonstrated as a compact building block, that to a large extent realizes the transmit path in a closed-loop mmWave transmitter. The evaluation of an successive-approximation register (SAR) analog-to-digital converter (ADC) is also presented in this thesis. Methods for connecting simulated and measured performance has been studied in order to achieve a better understanding about the alternating comparator topology.These contributions show great potential for enabling closed-loop mmWave transmitters for massive MIMO transmitter realizations

Cross-Layer Optimization for Power-Efficient and Robust Digital Circuits and Systems

With the increasing digital services demand, performance and power-efficiency become vital requirements for digital circuits and systems. However, the enabling CMOS technology scaling has been facing significant challenges of device uncertainties, such as process, voltage, and temperature variations. To ensure system reliability, worst-case corner assumptions are usually made in each design level. However, the over-pessimistic worst-case margin leads to unnecessary power waste and performance loss as high as 2.2x. Since optimizations are traditionally confined to each specific level, those safe margins can hardly be properly exploited. To tackle the challenge, it is therefore advised in this Ph.D. thesis to perform a cross-layer optimization for digital signal processing circuits and systems, to achieve a global balance of power consumption and output quality. To conclude, the traditional over-pessimistic worst-case approach leads to huge power waste. In contrast, the adaptive voltage scaling approach saves power (25% for the CORDIC application) by providing a just-needed supply voltage. The power saving is maximized (46% for CORDIC) when a more aggressive voltage over-scaling scheme is applied. These sparsely occurred circuit errors produced by aggressive voltage over-scaling are mitigated by higher level error resilient designs. For functions like FFT and CORDIC, smart error mitigation schemes were proposed to enhance reliability (soft-errors and timing-errors, respectively). Applications like Massive MIMO systems are robust against lower level errors, thanks to the intrinsically redundant antennas. This property makes it applicable to embrace digital hardware that trades quality for power savings.Comment: 190 page