Compact Modeling for a Double Gate MOSFET

MOSFETs (metal-oxide-silicon field-effect transistors) are an integral part of modern electronics. Improved designs are currently under investigation, and one that is promising is the double gate MOSFET. Understanding device characteristics is critical for the design of MOSFETs as part of design tools for integrated circuits such as SPICE. Current methods involve the numerical solution of PDEs governing electron transport. Numerical solutions are accurate, but do not provide an appropriate way to optimize the design of the device, nor are they suitable for use in chip simulation software such as SPICE. As chips contain more and more transistors, this problem will get more and more acute. There is hence a need for analytic solutions of the equations governing the performance of MOSFETs, even if these are approximate. Almost all solutions in the literature treat the long-channel case (thin devices) for which the PDEs reduce to ODEs. The goal of this problem is to produce analytical solutions based on the underlying PDEs that are rapid to compute (e.g. require solving only a small number of algebraic equations rather than systems of PDEs). Guided by asymptotic analysis, a fast numerical procedure has been developed to obtain approximate solutions of the governing PDEs governing MOSFET properties, namely electron density, Fermi potential and electrostatic potential. The approach depends on the channel’s being long enough, and appears accurate in this limit

The Modern FPGA as Discriminator, TDC and ADC

Recent generations of Field Programmable Gate Arrays (FPGAs) have become indispensible tools for complex state machine control and signal processing, and now routinely incorporate CPU cores to allow execution of user software code. At the same time, their exceptional performance permits low-power implementation of functionality previously the exclusive domain of dedicated analog electronics. Specific examples presented here use FPGAs as discriminator, time-to-digital (TDC) and analog-to-digital converter (ADC). All three cases are examples of instrumentation for current or future astroparticle experiments.Comment: 7 pages, v3 minor JINST editorial correction

The Design And Vlsi Implementation Of Digital Arithmatic Processors - A Case Study Of A Generalized Pipeline Cellular Array

A generalized pipeline array appeared in IEEE transaction in 1974. The array appeared in a few textbooks on computer arithmetic. From time to time, a number of papers appeared which reflected the modifications of this array. The objective of this thesis is to present the design and VLSI implementation of this array, which can add, subtract, multiply, divide, square and square root of binary numbers. In this thesis, we suggest a step-by-step procedure by which the design can be sent to MOSIS and to get the fabricated chip back. The array has been extended from 5 rows to 7 rows so that the extended operations can be performed. In particular, a procedure is developed by which the design and the implementation methodologies are suitable for 40 pin and 500 nm technologies. An algorithm has been developed by which one can predict and advance the maximum size and performance of the array. In addition, to increase data processing throughput, the extension of pipelining is conducted based on the original design. It is hoped that the design and implementation done here will go a long way in the development of advanced processors

Interfaces, modularity and ecosystem emergence: How DARPA modularized the semiconductor ecosystem

Scholars have identified the pivotal role that modularity plays in promoting innovation. Modularity affects industry structure by breaking up the value chain along technical interfaces, thereby allowing new entrants to specialize and innovate. Less well-understood is where modularity comes from. Firms seem to behave consistently with the theory in some settings, especially the information technology sector, but not in others, such as automobiles. Here we show how the government has a role to play in generating open interfaces needed for modularity, utilizing a case study of the semiconductor industry from 1970 to 1980. We show how the Defense Department\u27s support for this effort aligned with its mission-based interest in semiconductors. We thus contribute a new source of open standards to the modularity literature, as well as a new analytical perspective to the public research funding literature

Scale Control Processor Test-Chip

We are investigating vector-thread architectures which provide competitive performance and efficiency across a broad class of application domains. Vector-thread architectures unify data-level, thread-level, and instruction-level parallelism, providing new ways of parallelizing codes that are difficult to vectorize or that incur excessive synchronization costs when multithreaded. To illustrate these ideas we have developed the Scale processor, which is an example of a vector-thread architecture designed for low-power and high-performance embedded systems. The prototype includes a single-issue 32-bit RISC control processor, a vector-thread unit which supports up to 128 virtual processor threads and can execute up to 16 instructions per cycle, and a 32 KB shared primary cache.Since the Scale Vector-Thread Processor is a large and complex design (especially for an academic project), we first designed and fabricated the Scale Test Chip (STC1). STC1 includes a simplified version of the Scale control processor, 8 KB of RAM, a host interface, and a custom clock generator. STC1 helped mitigate the risk involved in fabricating the full Scale chip in several ways. First, we were able to establish and test our CAD toolflow. Our toolflow included several custom tools which had not previously been used in any tapeouts. Second, we were able to better characterize our target package and process. For example, STC1 enabled us to better correlate the static timing numbers from our CAD tools with actual silicon and also to characterize the expected rise/fall times of our external signal pins. Finally, STC1 allowed us to test our custom clock generator. We used our experiences with STC1 to help us implement the Scale vector-thread processor. Scale was taped out on October 15, 2006 and it is currently being fabricated through MOSIS. This report discusses the fabrication of STC1 and presents power and performance results

Barnes Hospital Bulletin

https://digitalcommons.wustl.edu/bjc_barnes_bulletin/1201/thumbnail.jp

Teaching integrated circuit and semiconductor device design in New Zealand: the University of Canterbury approach

Teaching the practical aspects of device and chip design in New Zealand presents many problems, including high manufacturing costs, long lead times, and the lack of local industry strength. Nonetheless, it is possible to overcome these issues. This paper describes the courses in these areas at the University of Canterbury, including a practical IC design project that has been running successfully for the past four years. The IC design project takes final year students through a full custom design using modern design tools and fabrication processes. The design is quite straightforward — a 4-bit arithmetic logic unit — but it emphasises the importance of design, simulation and testing. The final circuits contain a few hundred transistors, so good practice is essential. Twelve designs are integrated on to a single chip to keep costs down, and individual designs are addressed via multiplexers. The designs are fabricated using a 0.5 micron process, accessed through a multi-project vendor (MOSIS). Getting chips back from a manufacturer is significantly more motivating for the students than just performing a paper design

MICROELECTRONICS AND EMBEDDED SYSTEMS DESIGN AND DEVELOPMENT: TOOLS FOR ACHIEVING NIGERIA'S VISION:20:2020

This paper presents development and diffusion of microelectronics and embedded systems technologies in Nigeria as key tools for achieving Nigeria’s Vision20:2020. The Vision20:2020 objectives and necessary developmental steps (Investments in technology driven Agriculture and Hi-tech manufacturing industries to boost the Nation’s GDP and GNI) identified as vital to its achievement are discussed. Researchers have observed that appropriate diffusion of microelectronics and embedded systems technologies enhance economic activities and transitions developing economies from consuming to creating. They drive all key sectors of the 21century, hence the paper argues that they will provide Nigeria with the necessary growth engine needed to produce an accelerated economic growth. A road map to facilitate development and diffusion of these technologies in Nigeria was clearly articulated. With appropriate Government policies, support from all stake holders and the will to stick to the implementation plans, in place, sustenance of achieved development and economic growth will be guaranteed

Prenatal education for congenital toxoplasmosis

Congenital toxoplasmosis is considered a rare but potentially severe infection. Prenatal education about congenital toxoplasmosis could be the most efficient and least harmful intervention, yet its effectiveness is uncertain