20 research outputs found
Π‘ΡΠ°ΡΠΈΡΠ΅ΡΠΊΠ°Ρ ΠΏΡΠΎΠ²Π΅ΡΠΊΠ° ΠΊΠΎΡΡΠ΅ΠΊΡΠ½ΠΎΡΡΠΈ ΡΠ°Π·Π΄Π΅Π»Π΅Π½ΠΈΡ ΡΠ΅ΡΡΡΡΠΎΠ² Π² ΡΠΈΡΡΠ΅ΠΌΠ°Ρ ΡΠ΅Π°Π»ΡΠ½ΠΎΠ³ΠΎ Π²ΡΠ΅ΠΌΠ΅Π½ΠΈ
Among issues which arise when developing software complexes for real-time systems (RTS) one should resolve common multi-task system issues of ensuring logical correctness of the system being created (preserving the integrity of informational resources, eliminating the possibility of mutual task blocking), as well as issues of ensuring dynamic correctness, specific for RTS (feasibility of the application tasks). In the long run, resolving these issues is reduced to checking the correctness of how synchronizing operators which ensure consistent execution of application tasks are scattered in the task bodies. In order to perform such checking statically, models which represent the scattering of synchronizing operators in application tasks are constructed.
In this paper several methods of processing such models are proposed which are based on constructing special multi-partite graphs β graphs of synchronizing operator dependencies. Two varieties of such graphs are resented: a) graphs of bundles, which ensure verification of logical correctness of multi-task applications (correctness of intersections of critical interval pairs); and b) graphs of bundles and critical intervals, which ensure verification of dynamic correctness of RTS applications.Π ΡΡΠ΄Ρ Π²ΠΎΠΏΡΠΎΡΠΎΠ², Π²ΠΎΠ·Π½ΠΈΠΊΠ°ΡΡΠΈΡ
Π² Ρ
ΠΎΠ΄Π΅ ΡΠ°Π·ΡΠ°Π±ΠΎΡΠΊΠΈ ΠΏΡΠΎΠ³ΡΠ°ΠΌΠΌΠ½ΡΡ
ΠΊΠΎΠΌΠΏΠ»Π΅ΠΊΡΠΎΠ² Π΄Π»Ρ Π‘Π Π, Π½Π΅ΠΎΠ±Ρ
ΠΎΠ΄ΠΈΠΌΠΎ ΡΠ΅ΡΠ°ΡΡ ΠΊΠ°ΠΊ ΠΎΠ±ΡΠΈΠ΅ Π΄Π»Ρ ΠΌΠ½ΠΎΠ³ΠΎΠ·Π°Π΄Π°ΡΠ½ΡΡ
ΡΠΈΡΡΠ΅ΠΌ Π²ΠΎΠΏΡΠΎΡΡ ΠΎΠ±Π΅ΡΠΏΠ΅ΡΠ΅Π½ΠΈΡ Π»ΠΎΠ³ΠΈΡΠ΅ΡΠΊΠΎΠΉ ΠΊΠΎΡΡΠ΅ΠΊΡΠ½ΠΎΡΡΠΈ ΡΠΎΠ·Π΄Π°Π²Π°Π΅ΠΌΠΎΠΉ ΡΠΈΡΡΠ΅ΠΌΡ (ΡΠΎΡ
ΡΠ°Π½Π΅Π½ΠΈΠ΅ ΡΠ΅Π»ΠΎΡΡΠ½ΠΎΡΡΠΈ ΠΈΠ½ΡΠΎΡΠΌΠ°ΡΠΈΠΎΠ½Π½ΡΡ
ΡΠ΅ΡΡΡΡΠΎΠ², ΠΈΡΠΊΠ»ΡΡΠ΅Π½ΠΈΡ Π²ΠΎΠ·ΠΌΠΎΠΆΠ½ΠΎΡΡΠΈ Π²Π·Π°ΠΈΠΌΠ½ΠΎΠ³ΠΎ Π±Π»ΠΎΠΊΠΈΡΠΎΠ²Π°Π½ΠΈΡ Π·Π°Π΄Π°Ρ), ΡΠ°ΠΊ ΠΈ ΡΠΏΠ΅ΡΠΈΡΠΈΡΠ΅ΡΠΊΠΈΠ΅ Π΄Π»Ρ Π‘Π Π Π²ΠΎΠΏΡΠΎΡΡ Π΄ΠΈΠ½Π°ΠΌΠΈΡΠ΅ΡΠΊΠΎΠΉ ΠΊΠΎΡΡΠ΅ΠΊΡΠ½ΠΎΡΡΠΈ (ΡΠ²ΠΎΠ΅Π²ΡΠ΅ΠΌΠ΅Π½Π½ΠΎΡΡΠΈ ΠΈΡΠΏΠΎΠ»Π½Π΅Π½ΠΈΡ Π·Π°Π΄Π°Ρ). Π Π΅ΡΠ΅Π½ΠΈΠ΅ ΡΡΠΈΡ
Π²ΠΎΠΏΡΠΎΡΠΎΠ² Π² ΠΊΠΎΠ½Π΅ΡΠ½ΠΎΠΌ ΡΡΠ΅ΡΠ΅ ΡΠ²ΠΎΠ΄ΠΈΡΡΡ ΠΊ ΠΏΡΠΎΠ²Π΅ΡΠΊΠ΅ ΠΊΠΎΡΡΠ΅ΠΊΡΠ½ΠΎΡΡΠΈ ΡΠ°Π·ΠΌΠ΅ΡΠ΅Π½ΠΈΡ Π² ΡΠ΅Π»Π΅ ΠΊΠ°ΠΆΠ΄ΠΎΠΉ ΠΈΠ· Π·Π°Π΄Π°Ρ ΡΠΈΠ½Ρ
ΡΠΎΠ½ΠΈΠ·ΠΈΡΡΡΡΠΈΡ
ΠΎΠΏΠ΅ΡΠ°ΡΠΎΡΠΎΠ², ΠΎΠ±Π΅ΡΠΏΠ΅ΡΠΈΠ²Π°ΡΡΠΈΡ
ΡΠΎΠ³Π»Π°ΡΠΎΠ²Π°Π½Π½ΠΎΠ΅ ΠΈΡΠΏΠΎΠ»Π½Π΅Π½ΠΈΠ΅ Π·Π°Π΄Π°Ρ. Π’Π°ΠΊΠ°Ρ ΠΏΡΠΎΠ²Π΅ΡΠΊΠ° ΠΊΠΎΡΡΠ΅ΠΊΡΠ½ΠΎΡΡΠΈ ΠΎΡΡΡΠ΅ΡΡΠ²Π»ΡΠ΅ΡΡΡ ΡΡΠ°ΡΠΈΡΠ΅ΡΠΊΠΈ. Π‘ ΡΡΠΎΠΉ ΡΠ΅Π»ΡΡ ΡΡΡΠΎΡΡΡΡ ΠΌΠΎΠ΄Π΅Π»ΠΈ, ΠΎΡΡΠ°ΠΆΠ°ΡΡΠΈΠ΅ ΡΠ°Π·ΠΌΠ΅ΡΠ΅Π½ΠΈΠ΅ ΡΠΈΠ½Ρ
ΡΠΎΠ½ΠΈΠ·ΠΈΡΡΡΡΠΈΡ
ΠΎΠΏΠ΅ΡΠ°ΡΠΎΡΠΎΠ² Π² Π·Π°Π΄Π°ΡΠ°Ρ
ΠΏΡΠΈΠ»ΠΎΠΆΠ΅Π½ΠΈΡ.
Π Π½Π°ΡΡΠΎΡΡΠ΅ΠΉ ΡΡΠ°ΡΡΠ΅ ΠΏΡΠ΅Π΄Π»Π°Π³Π°ΡΡΡΡ ΠΌΠ΅ΡΠΎΠ΄Ρ ΠΎΠ±ΡΠ°Π±ΠΎΡΠΊΠΈ ΡΠ°ΠΊΠΈΡ
ΠΌΠΎΠ΄Π΅Π»Π΅ΠΉ ΠΏΠΎΡΡΠ΅Π΄ΡΡΠ²ΠΎΠΌ ΠΏΠΎΡΡΡΠΎΠ΅Π½ΠΈΡ ΡΠΏΠ΅ΡΠΈΠ°Π»ΡΠ½ΡΡ
ΠΌΠ½ΠΎΠ³ΠΎΠ΄ΠΎΠ»ΡΠ½ΡΡ
Π³ΡΠ°ΡΠΎΠ² β Π³ΡΠ°ΡΠΎΠ² Π·Π°Π²ΠΈΡΠΈΠΌΠΎΡΡΠ΅ΠΉ ΡΠΈΠ½Ρ
ΡΠΎΠ½ΠΈΠ·ΠΈΡΡΡΡΠΈΡ
ΠΎΠΏΠ΅ΡΠ°ΡΠΎΡΠΎΠ². ΠΡΠ΅Π΄ΡΡΠ°Π²Π»ΡΡΡΡΡ Π΄Π²Π΅ ΡΠ°Π·Π½ΠΎΠ²ΠΈΠ΄Π½ΠΎΡΡΠΈ ΡΠ°ΠΊΠΈΡ
Π³ΡΠ°ΡΠΎΠ²: Π°) Π³ΡΠ°ΡΡ ΡΠ²ΡΠ·ΠΎΠΊ, ΠΎΠ±Π΅ΡΠΏΠ΅ΡΠΈΠ²Π°ΡΡΠΈΠ΅ ΠΏΡΠΎΠ²Π΅ΡΠΊΡ Π»ΠΎΠ³ΠΈΡΠ΅ΡΠΊΠΎΠΉ ΠΊΠΎΡΡΠ΅ΠΊΡΠ½ΠΎΡΡΠΈ ΠΌΠ½ΠΎΠ³ΠΎΠ·Π°Π΄Π°ΡΠ½ΡΡ
ΠΏΡΠΈΠ»ΠΎΠΆΠ΅Π½ΠΈΠΉ, (ΠΊΠΎΡΡΠ΅ΠΊΡΠ½ΠΎΡΡΡ ΠΏΠ΅ΡΠ΅ΡΠ΅ΡΠ΅Π½ΠΈΠΉ ΠΏΠ°Ρ ΠΊΡΠΈΡΠΈΡΠ΅ΡΠΊΠΈΡ
ΠΈΠ½ΡΠ΅ΡΠ²Π°Π»ΠΎΠ²); ΠΈ Π±) Π³ΡΠ°ΡΡ ΡΠ²ΡΠ·ΠΎΠΊ ΠΈ ΠΊΡΠΈΡΠΈΡΠ΅ΡΠΊΠΈΡ
ΠΈΠ½ΡΠ΅ΡΠ²Π°Π»ΠΎΠ², ΠΎΠ±Π΅ΡΠΏΠ΅ΡΠΈΠ²Π°ΡΡΠΈΠ΅ ΠΏΡΠΎΠ²Π΅ΡΠΊΡ Π΄ΠΈΠ½Π°ΠΌΠΈΡΠ΅ΡΠΊΠΎΠΉ ΠΊΠΎΡΡΠ΅ΠΊΡΠ½ΠΎΡΡΠΈ ΠΏΡΠΈΠ»ΠΎΠΆΠ΅Π½ΠΈΠΉ Π΄Π»Ρ Π‘Π Π
Π’ΡΠ°Π½Π·ΠΈΡΠΈΠ²Π½ΠΎΠ΅ Π½Π°ΡΠ»Π΅Π΄ΠΎΠ²Π°Π½ΠΈΠ΅ ΠΏΡΠΈΠΎΡΠΈΡΠ΅ΡΠΎΠ² Π² ΠΌΠ½ΠΎΠ³ΠΎΠ·Π°Π΄Π°ΡΠ½ΡΡ ΠΏΡΠΈΠ»ΠΎΠΆΠ΅Π½ΠΈΡΡ ΡΠ΅Π°Π»ΡΠ½ΠΎΠ³ΠΎ Π²ΡΠ΅ΠΌΠ΅Π½ΠΈ
Control procedures for accessing shared resources in multi-task real-time software applications are analyzed. Two approaches to preventing priority inversion β basic and transitive procedures of priority inheritance β are analyzed in detail. To illustrate the considered notions and statements, concrete examples of multi-task application configurations are provided along with their execution diagrams under particular scenarios of system events, which demonstrate insufficient response time of tasks with sufficient computing resources and even mutual task clinches. The nomenclature of attributes to be included into task and resource descriptors for task management with the two priority inheritance procedures is proposed. The sufficient conditions for the basic procedure to prevent priority inheritance are formulated. The procedure of transitive priority inheritance is demonstrated to be capable of detecting a mutual task clinch in the application.Π Π°ΡΡΠΌΠ°ΡΡΠΈΠ²Π°ΡΡΡΡ ΠΌΠ΅ΡΠΎΠ΄Ρ ΠΊΠΎΠ½ΡΡΠΎΠ»Ρ Π΄ΠΎΡΡΡΠΏΠ° Π·Π°Π΄Π°Ρ ΠΊ ΡΠ°Π·Π΄Π΅Π»ΡΠ΅ΠΌΡΠΌ ΡΠ΅ΡΡΡΡΠ°ΠΌ Π² ΠΏΡΠΎΠ³ΡΠ°ΠΌΠΌΠ½ΡΡ
ΠΏΡΠΈΠ»ΠΎΠΆΠ΅Π½ΠΈΡΡ
Π΄Π»Ρ ΡΠΈΡΡΠ΅ΠΌ ΡΠ΅Π°Π»ΡΠ½ΠΎΠ³ΠΎ Π²ΡΠ΅ΠΌΠ΅Π½ΠΈ. ΠΡΠΈΠ²ΠΎΠ΄ΠΈΡΡΡ Π΄Π΅ΡΠ°Π»ΡΠ½ΠΎΠ΅ ΠΏΡΠ΅Π΄ΡΡΠ°Π²Π»Π΅Π½ΠΈΠ΅ Π΄Π²ΡΡ
ΠΏΡΠΎΡΠ΅Π΄ΡΡ Π½Π°ΡΠ»Π΅Π΄ΠΎΠ²Π°Π½ΠΈΡ ΠΏΡΠΈΠΎΡΠΈΡΠ΅ΡΠΎΠ² Π·Π°Π΄Π°Ρ: Π½Π΅ΠΏΠΎΡΡΠ΅Π΄ΡΡΠ²Π΅Π½Π½ΠΎΠΉ ΠΈ ΡΡΠ°Π½Π·ΠΈΡΠΈΠ²Π½ΠΎΠΉ. Π‘ΡΠΎΡΠΌΡΠ»ΠΈΡΠΎΠ²Π°Π½Ρ Π΄ΠΎΡΡΠ°ΡΠΎΡΠ½ΡΠ΅ ΡΡΠ»ΠΎΠ²ΠΈΡ, ΠΏΡΠΈ ΠΊΠΎΡΠΎΡΡΡ
ΠΏΡΠΈΠΌΠ΅Π½Π΅Π½ΠΈΠ΅ Π½Π΅ΠΏΠΎΡΡΠ΅Π΄ΡΡΠ²Π΅Π½Π½ΠΎΠΉ ΠΏΡΠΎΡΠ΅Π΄ΡΡΡ ΠΏΡΠ΅Π΄ΠΎΡΠ²ΡΠ°ΡΠ°Π΅Ρ ΠΈΠ½Π²Π΅ΡΡΠΈΡ ΠΏΡΠΈΠΎΡΠΈΡΠ΅ΡΠΎΠ². ΠΡΠ΅Π΄Π»ΠΎΠΆΠ΅Π½Π° ΠΌΠΎΠ΄ΠΈΡΠΈΠΊΠ°ΡΠΈΡ ΡΡΠ°Π½Π·ΠΈΡΠΈΠ²Π½ΠΎΠΉ ΠΏΡΠΎΡΠ΅Π΄ΡΡΡ ΡΠ½ΠΈΠΌΠ°ΡΡΠ°Ρ ΠΈΠ·Π²Π΅ΡΡΠ½ΡΠ΅ ΠΎΠ³ΡΠ°Π½ΠΈΡΠ΅Π½ΠΈΡ Π½Π° ΡΡΡΡΠΊΡΡΡΡ ΠΏΡΠΈΠ»ΠΎΠΆΠ΅Π½ΠΈΡ, Π½Π°ΠΊΠ»Π°Π΄ΡΠ²Π°Π΅ΠΌΡΠ΅ Π΅Π΅ ΡΡΠ°Π΄ΠΈΡΠΈΠΎΠ½Π½ΠΎΠΉ ΡΠ΅Π°Π»ΠΈΠ·Π°ΡΠΈΠ΅ΠΉ. ΠΡΠ° ΠΌΠΎΠ΄ΠΈΡΠΈΠΊΠ°ΡΠΈΡ, ΠΊΡΠΎΠΌΠ΅ ΡΠΎΠ³ΠΎ, ΠΎΠ±Π΅ΡΠΏΠ΅ΡΠΈΠ²Π°Π΅Ρ Π΄ΠΈΠ½Π°ΠΌΠΈΡΠ΅ΡΠΊΠΎΠ΅ ΠΎΠ±Π½Π°ΡΡΠΆΠ΅Π½ΠΈΠ΅ Π½Π΅ΠΊΠΎΡΡΠ΅ΠΊΡΠ½ΡΡ
ΡΠΈΡΡΠ°ΡΠΈΠΉ ΡΠΈΠΏΠ° Π²Π·Π°ΠΈΠΌΠ½ΠΎΠ³ΠΎ Π±Π»ΠΎΠΊΠΈΡΠΎΠ²Π°Π½ΠΈΡ Π·Π°Π΄Π°Ρ Ρ Π²ΠΎΠ·ΠΌΠΎΠΆΠ½ΠΎΡΡΡΡ Π·Π°ΠΏΠ»Π°Π½ΠΈΡΠΎΠ²Π°Π½Π½ΠΎΠΉ ΡΠ΅Π°ΠΊΡΠΈΠΈ Π½Π° ΡΠ°ΠΊΠΈΠ΅ ΡΠΈΡΡΠ°ΡΠΈΠΈ
A Workload Generator for Evaluating SMT Real-Time Systems
[EN] Real-time tasks have experience a significant complexity increase in the last years. We can find examples of real-time tasks in nowadays systems that control self-driving cars or multimedia systems, among others. To cope with the high performance requirements of such systems, real-time systems are moving from simple in-order processor to complex out-of-order multicore processors. Furthermore, we expect real-time systems to use simultaneous multithreading (SMT) processors in a near future since these architectures address two key design concerns of embedded systems, that is, they provide higher performance and power efficiency than single-threaded multicores.
The main drawback that multicores and SMT architectures present from a real-time perspective is that they implement shared resources. Single-threaded multicores usually share the main memory and the LLC, and SMT processor share additionally most of the microarchitectural core resources. Processes running concurrently can interfere in the shared resources, which increases the performance variability and predictability of these systems. We expect an increasing effort in the next years to mitigate these drawbacks and implement real-time systems with multicore SMT processors.
Workload generation is a tedious and time-consuming task in the real-time research field because the workloads dispose of many parameters that should be correctly adjusted to provide flexible and representative workloads. Typically used workload generators, however, fail when designing workloads for theses architectures because they are not aware of the architectural characteristics of SMT systems. In this paper we present the task class-based (TCB) workload generator aimed at providing workloads to evaluate real-time systems with SMT multicore processors in an ease and automatized way.FuriΓ³ Novejarque, C.; Feliu-PΓ©rez, J.; Petit MartΓ, SV.; Duro-GΓ³mez, J.; Sahuquillo BorrΓ‘s, J. (2018). A Workload Generator for Evaluating SMT Real-Time Systems. IEEE Computer Society. 367-374. doi:10.1109/HPCS.2018.00067S36737
Schedulability analysis of global scheduling algorithms on multiprocessor platforms
This paper addresses the schedulability problem of periodic and sporadic real-time task sets with constrained deadlines preemptively scheduled on a multiprocessor platform composed by identical processors. We assume that a global work-conserving scheduler is used and migration from one processor to another is allowed during a task lifetime. First, a general method to derive schedulability conditions for multiprocessor real-time systems will be presented. The analysis will be applied to two typical scheduling algorithms: earliest deadline first (EDF) and fixed priority (FP). Then, the derived schedulability conditions will be tightened, refining the analysis with a simple and effective technique that significantly improves the percentage of accepted task sets. The effectiveness of the proposed test is shown through an extensive set of synthetic experiments
Best Speed Fit EDF Scheduling for Performance Asymmetric Multiprocessors
In order to improve the performance of a real-time system, asymmetric multiprocessors have been proposed. The benefits of improved system performance and reduced power consumption from such architectures cannot be fully exploited unless suitable task scheduling and task allocation approaches are implemented at the operating system level. Unfortunately, most of the previous research on scheduling algorithms for performance asymmetric multiprocessors is focused on task priority assignment. They simply assign the highest priority task to the fastest processor. In this paper, we propose BSF-EDF (best speed fit for earliest deadline first) for performance asymmetric multiprocessor scheduling. This approach chooses a suitable processor rather than the fastest one, when allocating tasks. With this proposed BSF-EDF scheduling, we also derive an effective schedulability test
Schedulability analysis of global scheduling algorithms on multiprocessor platforms
This paper addresses the schedulability problem of periodic and sporadic real-time task sets with constrained deadlines preemptively scheduled on a multiprocessor platform composed by identical processors. We assume that a global work-conserving scheduler is used and migration from one processor to another is allowed during a task lifetime. First, a general method to derive schedulability conditions for multiprocessor real-time systems will be presented. The analysis will be applied to two typical scheduling algorithms: earliest deadline first (EDF) and fixed priority (FP). Then, the derived schedulability conditions will be tightened, refining the analysis with a simple and effective technique that significantly improves the percentage of accepted task sets. The effectiveness of the proposed test is shown through an extensive set of synthetic experiments
Parallelizing with BDSC, a resource-constrained scheduling algorithm for shared and distributed memory systems
International audienceWe introduce a new parallelization framework for scientific computing based on BDSC, an efficient automatic scheduling algorithm for parallel programs in the presence of resource constraints on the number of processors and their local memory size. BDSC extends Yang and Gerasoulis's Dominant Sequence Clus-tering (DSC) algorithm; it uses sophisticated cost models and addresses both shared and distributed parallel memory architectures. We describe BDSC, its integration within the PIPS compiler infrastructure and its application to the parallelization of four well-known scientific applications: Harris, ABF, equake and IS. Our experiments suggest that BDSC's focus on efficient resource man-agement leads to significant parallelization speedups on both shared and dis-tributed memory systems, improving upon DSC results, as shown by the com-parison of the sequential and parallelized versions of these four applications running on both OpenMP and MPI frameworks
Optimal virtual cluster-based multiprocessor scheduling
Scheduling of constrained deadline sporadic task systems on multiprocessor platforms is an area which has received much attention in the recent past. It is widely believed that finding an optimal scheduler is hard, and therefore most studies have focused on developing algorithms with good processor utilization bounds. These algorithms can be broadly classified into two categories: partitioned scheduling in which tasks are statically assigned to individual processors, and global scheduling in which each task is allowed to execute on any processor in the platform. In this paper we consider a third, more general, approach called cluster-based scheduling. In this approach each task is statically assigned to a processor cluster, tasks in each cluster are globally scheduled among themselves, and clusters in turn are scheduled on the multiprocessor platform. We develop techniques to support such cluster-based scheduling algorithms, and also consider properties that minimize total processor utilization of individual clusters. In the last part of this paper, we develop new virtual cluster-based scheduling algorithms. For implicit deadline sporadic task systems, we develop an optimal scheduling algorithm that is neither Pfair nor ERfair. We also show that the processor utilization bound of us-edf{m/(2mβ1)} can be improved by using virtual clustering. Since neither partitioned nor global strategies dominate over the other, cluster-based scheduling is a natural direction for research towards achieving improved processor utilization bounds