4 research outputs found
Runtime methods for energy-efficient, image processing using significance driven learning.
Ph. D. Thesis.Image and Video processing applications are opening up a whole
range of opportunities for processing at the "edge" or IoT applications
as the demand for high accuracy processing high resolution images
increases. However this comes with an increase in the quantity of data
to be processed and stored, thereby causing a significant increase in
the computational challenges. There is a growing interest in developing
hardware systems that provide energy efficient solutions to this
challenge. The challenges in Image Processing are unique because the
increase in resolution, not only increases the data to be processed but
also the amount of information detail scavenged from the data is also
greatly increased. This thesis addresses the concept of extracting the
significant image information to enable processing the data intelligently
within a heterogeneous system.
We propose a unique way of defining image significance, based on
what causes us to react when something "catches our eye", whether it
be static or dynamic, whether it be in our central field of focus or our
peripheral vision. This significance technique proves to be a relatively
economical process in terms of energy and computational effort.
We investigate opportunities for further computational and energy
efficiency that are available by elective use of heterogeneous system
elements.
We utilise significance to adaptively select regions of interest for selective
levels of processing dependent on their relative significance.
We further demonstrate that exploiting the computational slack time
released by this process, we can apply throttling of the processor
speed to effect greater energy savings. This demonstrates a reduction
in computational effort and energy efficiency a process that we term
adaptive approximate computing.
We demonstrate that our approach reduces energy in a range of 50 to
75%, dependent on user quality demand, for a real-time performance
requirement of 10 fps for a WQXGA image, when compared with the
existing approach that is agnostic of significance. We further hypothesise
that by use of heterogeneous elements that savings up to 90%
could be achievable in both performance and energy when compared
with running OpenCV on the CPU alone
Investigation of reconfigurable-accuracy approximate adder designs for image processing applications
Ph. D. Thesis.In the last decades, integrated circuits with CMOS technology show
progressive scaling challenges of both increased power density and
power dissipation. Meanwhile, high-performance requirements of
current and future application operations show rapid demands of
computing resources like power. This design conflict has pushed
much effort to search for high performance and energy efficient
design approach, such as approximate computing.
Approximate computing exploits the error resilience of compute-
intensive applications such as image processing applications to
implement approximation design techniques with different levels
of abstractions and scalability. The basic principle is to relax the
strict accuracy requirements in favour of a lower design complexity,
thereby achieving more computational performance (i.e., speed)
and energy saving. The adder arithmetic unit is considered one
of the essential computational blocks in most of the applications.
As such, much effort has explored new designs of an efficient
approximate adder design.
This thesis presents an investigation into design enhancement,
novel approximate adder designs and implementation approaches.
The first approach introduces a modification to the error detection
technique of a popular configurable-accuracy approximate adder
design. The proposed lightweight error detection technique reduces
the required gates of the error detection circuit, thus, mitigating
the design area overhead. Furthermore, at the error correction
process of the adder, we have proposed an extensive error detection
while activating more than one correction stage concurrently. As a
result, this ensures achieving an optimum accuracy of outputs for
the worst case of quality requirements.
In general, approximate (speculative) adder designs use the seg-
mentation technique to divide the adder into multiple short length
sub-adders which operate in parallel. Hence, this would limit the
long chains of carry propagation and result in a better performance
operations. However, the use of overlapped parts of sub-adders
regarding a better carry speculation and then more accuracy be-
comes a significant challenge of a large design area overhead. The
second approach continues mitigating this challenge by present-
ing a novel and simpler adder dividing technique to a number of
sub-adders. The new method uses what is known as the carry-kill
signal for both limiting the carry propagation and applying adder
segmentation. Further, between every two adjacent sub-adders,
one AND gate and one XOR gate are used for carry speculation
and error (i.e., carry propagation) detection respectively. Thus, a
significant reduction of the design overhead has been achieved, yet,
with acceptable levels of output results accuracy. In the third final
approach, simple logic OR gates are used to build the approximate
adder while compensating the conventional full adders operation.
The resulted approximate adder design presents very low complex-
ity, high speed, and low power consumption. Furthermore, instead
of augmenting error recovery circuit, short bit-length exact adders
are used as correction stages to control the general level of output
quality (i.e., without error detection overhead). At the final correc-
tion stage, the proposed design would operate the same as an exact
adder.
To validate the efficiency of these approaches, a number of adders
with different bit-widths are designed and synthesized showing
considerable reductions in the critical delay, silicon area and more
savings in energy consumption, compared to other existing ap-
proaches. In addition to acceptable levels or output errors, which
are extensively analysed for each proposed design.
In this study, the proposed configurable adder designs exhibit
energy/quality trade-offs at a different number of correction stages.
These trade-offs can be effectively exploited to implement adders
in applications, where energy can be gracefully minimised within
the envelope of quality requirements. As such, designs implemen-
tation in an image processing application known as Gaussian blur
filter was introduced, demonstrating the loss in the image quality
at each error correction stage. The output images showed promis-
ing results to use the proposed designs for more energy-efficient
applications, where output quality requirements can be relaxed.Mutah Universit