Automated drowsiness detection for improved driving safety

Several approaches were proposed for the detection and prediction of drowsiness. The approaches can be categorized as estimating the fitness of duty, modeling the sleep-wake rhythms, measuring the vehicle based performance and online operator monitoring. Computer vision based online operator monitoring approach has become prominent due to its predictive ability of detecting drowsiness. Previous studies with this approach detect driver drowsiness primarily by making preassumptions about the relevant behavior, focusing on blink rate, eye closure, and yawning. Here we employ machine learning to datamine actual human behavior during drowsiness episodes. Automatic classifiers for 30 facial actions from the Facial Action Coding system were developed using machine learning on a separate database of spontaneous expressions. These facial actions include blinking and yawn motions, as well as a number of other facial movements. In addition, head motion was collected through automatic eye tracking and an accelerometer. These measures were passed to learning-based classifiers such as Adaboost and multinomial ridge regression. The system was able to predict sleep and crash episodes during a driving computer game with 96% accuracy within subjects and above 90% accuracy across subjects. This is the highest prediction rate reported to date for detecting real drowsiness. Moreover, the analysis revealed new information about human behavior during drowsy drivin

Analysis of Power-aware Buffering Schemes in Wireless Sensor Networks

We study the power-aware buffering problem in battery-powered sensor networks, focusing on the fixed-size and fixed-interval buffering schemes. The main motivation is to address the yet poorly understood size variation-induced effect on power-aware buffering schemes. Our theoretical analysis elucidates the fundamental differences between the fixed-size and fixed-interval buffering schemes in the presence of data size variation. It shows that data size variation has detrimental effects on the power expenditure of the fixed-size buffering in general, and reveals that the size variation induced effects can be either mitigated by a positive skewness or promoted by a negative skewness in size distribution. By contrast, the fixed-interval buffering scheme has an obvious advantage of being eminently immune to the data-size variation. Hence the fixed-interval buffering scheme is a risk-averse strategy for its robustness in a variety of operational environments. In addition, based on the fixed-interval buffering scheme, we establish the power consumption relationship between child nodes and parent node in a static data collection tree, and give an in-depth analysis of the impact of child bandwidth distribution on parent's power consumption. This study is of practical significance: it sheds new light on the relationship among power consumption of buffering schemes, power parameters of radio module and memory bank, data arrival rate and data size variation, thereby providing well-informed guidance in determining an optimal buffer size (interval) to maximize the operational lifespan of sensor networks

Messiah: An ITS drive safety application

This article describes a novel safety application based on the open source navigation software OsmAnd, which runs on the Android platform. The application offers vehicles with "smart navigation", and maintains a network of the vehicles that use our application. The process of network creation and maintenance is important as our application enables vehicles to communicate with one another to exchange useful information. The main function of the application is to inform vehicles of relevant vehicles approaching, termed as "administrative vehicles" in this article, and include ambulances, police cars and fire brigades. Based on the received information, our application notifies the driver, who can now take navigation decisions based on it. While developing the application, problems were found when attempting to create an Ad-hoc network. A solution to the problem of managing the Ad-hoc network has been proposed and is under development

Low Power Processor Architectures and Contemporary Techniques for Power Optimization – A Review

The technological evolution has increased the number of transistors for a given die area significantly and increased the switching speed from few MHz to GHz range. Such inversely proportional decline in size and boost in performance consequently demands shrinking of supply voltage and effective power dissipation in chips with millions of transistors. This has triggered substantial amount of research in power reduction techniques into almost every aspect of the chip and particularly the processor cores contained in the chip. This paper presents an overview of techniques for achieving the power efficiency mainly at the processor core level but also visits related domains such as buses and memories. There are various processor parameters and features such as supply voltage, clock frequency, cache and pipelining which can be optimized to reduce the power consumption of the processor. This paper discusses various ways in which these parameters can be optimized. Also, emerging power efficient processor architectures are overviewed and research activities are discussed which should help reader identify how these factors in a processor contribute to power consumption. Some of these concepts have been already established whereas others are still active research areas. © 2009 ACADEMY PUBLISHER

A hardware mechanism to reduce the energy consumption of the register file of in-order architectures

This paper introduces an efficient hardware approach to reduce the register file energy consumption by turning unused registers into a low power state. Bypassing the register fields of the fetch instruction to the decode stage allows the identification of registers required by the current instruction (instruction predecode) and allows the control logic to turn them back on. They are put into the low-power state after the instruction use. This technique achieves an 85% energy reduction with no performance penalty

Gavestinel does not improve outcome after acute intracerebral hemorrhage: an analysis from the GAIN International and GAIN Americas studies

<p><b>Background and Purpose:</b> Glycine Antagonist in Neuroprotection (GAIN) International and GAIN Americas trials were prospectively designed, randomized, placebo-controlled trials of gavestinel, a glycine-site antagonist and putative neuroprotectant drug administered within 6 hours of suspected ischemic or hemorrhagic stroke. Both trials reported that gavestinel was ineffective in ischemic stroke. This analysis reports the results in those with primary intracerebral hemorrhage.</p> <p><b>Methods:</b> The primary hypothesis was that gavestinel treatment did not alter outcome, measured at 3 months by the Barthel Index (BI), from acute intracerebral hemorrhage, based on pooled results from both trials. The BI scores were divided into 3 groups: 95 to 100 (independent), 60 to 90 (assisted independence), and 0 to 55 (dependent) or dead.</p> <p><b>Results:</b> In total, 3450 patients were randomized in GAIN International (N=1804) and GAIN Americas (N=1646). Of these, 571 were ultimately identified to have spontaneous intracerebral hematoma on baseline head computerized tomography scan. The difference in distribution of trichotomized BI scores at 3 months between gavestinel and placebo was not statistically significant (P=0.09). Serious adverse events were reported at similar rates in the 2 treatment groups.</p> <p><b>Conclusions:</b> These observations from the combined GAIN International and GAIN Americas trials suggest that gavestinel is not of substantial benefit or harm to patients with primary intracerebral hemorrhage. These findings are similar to results previously reported in patients with ischemic stroke.</p&gt