Layout Decomposition for Quadruple Patterning Lithography and Beyond

For next-generation technology nodes, multiple patterning lithography (MPL) has emerged as a key solution, e.g., triple patterning lithography (TPL) for 14/11nm, and quadruple patterning lithography (QPL) for sub-10nm. In this paper, we propose a generic and robust layout decomposition framework for QPL, which can be further extended to handle any general K-patterning lithography (K$>$4). Our framework is based on the semidefinite programming (SDP) formulation with novel coloring encoding. Meanwhile, we propose fast yet effective coloring assignment and achieve significant speedup. To our best knowledge, this is the first work on the general multiple patterning lithography layout decomposition.Comment: DAC'201

Scalable Multiple Patterning Layout Decomposition Implemented by a Distribution Evolutionary Algorithm

As the feature size of semiconductor technology shrinks to 10 nm and beyond, the multiple patterning lithography (MPL) attracts more attention from the industry. In this paper, we model the layout decomposition of MPL as a generalized graph coloring problem, which is addressed by a distribution evolutionary algorithm based on a population of probabilistic model (DEA-PPM). DEA-PPM can strike a balance between decomposition results and running time, being scalable for varied settings of mask number and lithography resolution. Due to its robustness of decomposition results, this could be an alternative technique for multiple patterning layout decomposition in next-generation technology nodes

High performance algorithms for large scale placement problem

Placement is one of the most important problems in electronic design automation (EDA). An inferior placement solution will not only affect the chip’s performance but might also make it nonmanufacturable by producing excessive wirelength, which is beyond available routing resources. Although placement has been extensively investigated for several decades, it is still a very challenging problem mainly due to that design scale has been dramatically increased by order of magnitudes and the increasing trend seems unstoppable. In modern design, chips commonly integrate millions of gates that require over tens of metal routing layers. Besides, new manufacturing techniques bring out new requests leading to that multi-objectives should be optimized simultaneously during placement. Our research provides high performance algorithms for placement problem. We propose (i) a high performance global placement core engine POLAR; (ii) an efficient routability-driven placer POLAR 2.0, which is an extension of POLAR to deal with routing congestion; (iii) an ultrafast global placer POLAR 3.0, which explore parallelism on POLAR and can make full use of multi-core system; (iv) some efficient triple patterning lithography (TPL) aware detailed placement algorithms

Lithography aware physical design and layout optimization for manufacturability

textAs technology continues to scale down, semiconductor manufacturing with 193nm lithography is greatly challenging because the required half pitch size is beyond the resolution limit. In order to bridge the gap between design requirements and manufacturing limitations, various resolution enhancement techniques have been proposed to avoid potentially problematic patterns and to improve product yield. In addition, co-optimization between design performance and manufacturability can further provide flexible and significant yield improvement, and it has become necessary for advanced technology nodes. This dissertation presents the methodologies to consider the lithography impact in different design stages to improve layout manufacturability. Double Patterning Lithography (DPL) has been a promising solution for sub-22nm node volume production. Among DPL techniques, self-aligned double patterning (SADP) provides good overlay controllability when two masks are not aligned perfectly. However, SADP process places several limitations on design flexibility and still exists many challenges in physical design stages. Starting from the early design stage, we analyze the standard cell designs and construct a set of SADP-aware cell placement candidates, and show that placement legalization based on this SADP awareness information can effectively resolve DPL conflicts. In the detailed routing stage, we propose a new routing cost formulation based on SADP-compliant routing guidelines, and achieve routing and layout decomposition simultaneously. In the case that limited routing perturbation is allowed, we propose a post-routing flow based on lithography simulation and lithography-aware design rules. Both routing methods, one in detailed routing stage and one in post routing stage, reduce DPL conflicts/violations significantly with negligible wire length impact. In the layout decomposition stage, layout modification is restricted and thus the manufacturability is even harder to guaranteed. By taking the advantage of complementary lithography, we present a new layout decomposition approach with e-beam cutting, which optimizes SADP overlay error and e-beam lithography throughput simultaneously. After the mask layout is defined, optical proximity correction (OPC) is one of the resolution enhancement techniques that is commonly required to compensate the image distortion from the lithography process. We propose an inverse lithography technique to solve the OPC problem considering design target and process window co-optimization. Our mask optimization is pixel based and thus can enable better contour fidelity. In the final physical verification stage, a complex and time-consuming lithography simulation needs to be performed to identify faulty patterns. We provide a classification method based on support vector machine and principle component analysis that detects lithographic hotspots efficiently and accurately.Electrical and Computer Engineerin

Layout decomposition for triple patterning lithography

Nowadays the semiconductor industry is continuing to advance the limits of physics as the feature size of the chip keeps shrinking. Products of the 22 nm technology node are already available on the market, and there are many ongoing research studies for the 14/10 nm technology nodes and beyond. Due to the physical limitations, the traditional 193 nm immersion lithography is facing huge challenges in fabricating such tiny features. Several types of next-generation lithography techniques have been discussed for years, such as {\em extreme ultra-violet} (EUV) lithography, {\em E-beam direct write}, and {\em block copolymer directed self-assembly} (DSA). However, the source power for EUV is still an unresolved issue. The low throughput of E-beam makes it impractical for massive productions. DSA is still under calibration in research labs and is not ready for massive industrial deployment. Traditionally features are fabricated under single litho exposure. As feature size becomes smaller and smaller, single exposure is no longer adequate in satisfying the quality requirements. {\em Double patterning lithography} (DPL) utilizes two litho exposures to manufacture features on the same layer. Features are assigned to two masks, with each mask going through a separate litho exposure. With one more mask, the effective pitch is doubled, thus greatly enhancing the printing resolution. Therefore, DPL has been widely recognized as a feasible lithography solution in the sub-22 nm technology node. However, as the technology continues to scale down to 14/10 nm and beyond, DPL begins to show its limitations as it introduces a high number of stitches, which increases the manufacturing cost and potentially leads to functional errors of the circuits. {\em Triple pattering lithography} (TPL) uses three masks to print the features on the same layer, which further enhances the printing resolution. It is a natural extension for DPL with three masks available, and it is one of the most promising solutions for the 14/10 nm technology node and beyond. In this thesis, TPL decomposition for standard-cell-based designs is extensively studied. We proposed a polynomial time triple patterning decomposition algorithm which guarantees finding a TPL decomposition if one exists. For complex designs with stitch candidates, our algorithm is able to find a solution with the optimal number of stitches. For standard-cell-based designs, there are additional coloring constraints where the same type of cell should be fabricated following the same pattern. We proposed an algorithm that is guaranteed to find a solution when one exists. The framework of the algorithm is also extended to pattern-based TPL decompositions, where the cost of a decomposition can be minimized given a library of different patterns. The polynomial time TPL algorithm is further optimized in terms of runtime and memory while keeping the solution quality unaffected. We also studied the TPL aware detailed placement problem, where our approach is guaranteed to find a legal detailed placement satisfying TPL coloring constraints as well as minimizing the {\em half-perimeter wire length} (HPWL). Finally, we studied the problem of performance variations due to mask misalignment in {\em multiple patterning decompositions} (MPL). For advanced technology nodes, process variations (mainly mask misalignment) have significant influences on the quality of fabricated circuits, and often lead to unexpected power/timing degenerations. Mask misalignment would complicate the way of simulating timing closure if engineers do not understand the underlying effects of mask misalignment, which only exists in multiple patterning decompositions. We mathematically proved the worst-case scenarios of coupling capacitance incurred by mask misalignment in MPL decompositions. A graph model is proposed which is guaranteed to compute the tight upper bound on the worst-case coupling capacitance of any MPL decompositions for a given layout

Design for Manufacturability in Advanced Lithography Technologies

As the technology nodes keep shrinking following Moore\u27s law, lithography becomes increasingly critical to the fabrication of integrated circuits. The 193nm ArF immersion lithography (193i) has been a common technique for manufacturing integrated circuits. However, the 193i with single exposure has finally reached its printability limit at the 28nm technology node. To keep the pace of Moore\u27s law, design for manufacturability (DFM) is demonstrated to be effective and cost-efficient. The concept of DFM is to modify the design of integrated circuits in order to make them more manufacturable. Tremendous efforts have been made for DFM in advanced lithography technologies. In general, the progress can be summarized in four directions. (1) Advanced lithography process by novel patterning techniques and next-generation lithography; (2) High performance lithography simulation approach in mask synthesis; (3) Physical design (PD) methodology with lithography manufacturability awareness; (4) Robust design flow integrating emerging PD challenges. Accordingly, we propose our research topics in those directions. (1) Throughput optimization for self-aligned double patterning (SADP) and e-beam lithography based manufacturing of 1D layout; (2) Design of efficient rasterization algorithm for mask patterns in inverse lithography technology (ILT); (3) SADP-aware detailed routing; (4) SADP-aware detailed routing with consideration of double via insertion and via manufacturability; (5) Pin accessibility driven detailed placement refinement. In our first research work, we investigate throughput optimization of 1D layout manufacturing. SADP is a mature lithography technique to print 1D gridded layout for advanced technologies. However, in 16nm technology node, trim mask pattern in SADP lithography process may not be printable using 193i along within a single exposure. A viable solution is to complement SADP with e-beam lithography. To order to increase the throughput of 1D layout manufacturing, we consider the problem of e-beam shot minimization subject to bounded line-end extension constraints. Two different approaches of utilizing the trim mask and e-beam to print a 1D layout are considered. The first approach is trimming by end cutting, in which trim mask and e-beam are used to chop up parallel lines at required locations by small fixed rectangles. The second approach is trimming by gap removal, in which trim mask and e-beam are used to rid of all unnecessary portions. We propose elegant integer linear program formulations for both approaches. Experimental results show that both integer linear program formulations can be solved efficiently and have a major speedup compared with previous related work. Furthermore, the pros and cons of the two approaches for manufacturing 1D layout are discussed. In our second research work, we focus on a critical problem of lithography simulation in the design of ILT mask. To reduce the complexity of modern lithography simulation, a widely used approach is to first rasterize the ILT mask before it is inputted to the simulation tool. Accordingly, we propose a high performance rasterization algorithm. The algorithm is based on a pre-computed look-up table. Every pixel in the rasterized image is firstly identified its category: exception or non-exception. Then convolution for every pixel can be performed by a single or multiple look-up table queries depending on its category. In addition, the proposed algorithm has shift invariant property and can be applied for all-angle mask patterns in ILT. Experimental results demonstrate that our approach can speedup conventional rasterization process by almost 500x while maintaining small variations in critical dimension. In our third research work, we concentrate on SADP-aware detailed routing. SADP is a promising manufacturing option for sub-22nm technology nodes due to its good overlay control. To ensure layout is manufacturable by SADP, it is necessary to consider it during layout configuration, e.g., detailed routing stage. However, SADP process is not intuitive in terms of mask design, and considering it during detailed routing stage is even more challenging. We investigate both of two popular types of SADP: spacer-is-dielectric and spacer-is-metal. Different from previous works, we apply the color pre-assignment idea and propose an elegant graph model which captures both routing and SADP manufacturing cost. They greatly simplify the problem to maintain SADP design rules during detailed routing. A negotiated congestion based rip-up and reroute scheme is applied to achieve good routability while maintaining SADP design rules. Our approach can be extended to consider other multiple patterning lithography during detailed routing, e.g., self-aligned quadruple patterning targeted at sub-10nm technology nodes. Compared with state-of-the-art academic SADP-aware detailed routers, we offer routing solution with better quality of result. In our fourth research work, we extend our SADP-aware detailed routing to consider other manufacturing issues. Both SADP and triple patterning lithography (TPL) are potential layout manufacturing techniques in 10nm technology node. While metal layers can be printed by SADP, via layer manufacturing requires TPL. Previous works on SADP-aware detailed routing do not automatically guarantee via layer are manufacturable by TPL. We extend our SADP-aware detailed routing to consider TPL manufacturability of via layer. Double via insertion is an effective method to improve yield and reliability in integrated circuits manufacturing. We also consider it in our SADP-aware detailed routing to further improve insertion rate. A problem of TPL-aware double via insertion in the post routing stage is proposed. It is solved by both integer linear programming and high-performance heuristic. Experimental results demonstrate that our SADP-aware detailed routing can ensure via layer are TPL manufacturable and improve double via insertion rate. In our last research work, we target at the enhancement of pin access. The significant increased number of routing design rules in advanced technologies has made pin access an emerging difficultly in detailed routing. Resolving pin access in detailed routing may be too late due to the fix pin locations. Thus, we consider pin access in earlier design stage, i.e., detailed placement stage, when perturbation of cell placement is allowed. A cost function is proposed to model pin access for each pin-to-pin connection in detailed routing. A two-phase detailed placement refinement is performed to improve pin access, and refinement techniques are limited to cell flipping, same-row adjacent cell swap and cell shifting. The problem is solved by dynamic programming and linear programming. Experimental results demonstrate that the proposed detailed placement refinement improve pin access and reduce the number of unroutable nets in detailed routing significantly