144 research outputs found

    Low Power Analog Processing for Ultra-High-Speed Receivers with RF Correlation

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    Ultra-high-speed data communication receivers (Rxs) conventionally require analog digital converters (ADC)s with high sampling rates which have design challenges in terms of adequate resolution and power. This leads to ultra-high-speed Rxs utilising expensive and bulky high-speed oscilloscopes which are extremely inefficient for demodulation, in terms of power and size. Designing energy-efficient mixed-signal and baseband units for ultra-high-speed Rxs requires a paradigm approach detailed in this paper that circumvents the use of power-hungry ADCs by employing low-power analog processing. The low-power analog Rx employs direct-demodulation with RF correlation using low-power comparators. The Rx is able to support multiple modulations with highest modulation of 16-QAM reported so far for direct-demodulation with RF correlation. Simulations using Matlab, Simulink R2020a® indicate sufficient symbol-error rate (SER) performance at a symbol rate of 8 GS/s for the 71 GHz Urban Micro Cell and 140 GHz indoor channels. Power analysis undertaken with current analog, hybrid and digital beamforming approaches requiring ADCs indicates considerable power savings. This novel approach can be adopted for ultra-high-speed Rxs envisaged for beyond fifth generation (B5G)/sixth generation (6G)/ terahertz (THz) communication without the power-hungry ADCs, leading to low-power integrated design solutions

    Frame Structure Design and Analysis for Millimeter Wave Cellular Systems

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    The millimeter-wave (mmWave) frequencies have attracted considerable attention for fifth generation (5G) cellular communication as they offer orders of magnitude greater bandwidth than current cellular systems. However, the medium access control (MAC) layer may need to be significantly redesigned to support the highly directional transmissions, ultra-low latencies and high peak rates expected in mmWave communication. To address these challenges, we present a novel mmWave MAC layer frame structure with a number of enhancements including flexible, highly granular transmission times, dynamic control signal locations, extended messaging and ability to efficiently multiplex directional control signals. Analytic formulae are derived for the utilization and control overhead as a function of control periodicity, number of users, traffic statistics, signal-to-noise ratio and antenna gains. Importantly, the analysis can incorporate various front-end MIMO capability assumptions -- a critical feature of mmWave. Under realistic system and traffic assumptions, the analysis reveals that the proposed flexible frame structure design offers significant benefits over designs with fixed frame structures similar to current 4G long-term evolution (LTE). It is also shown that fully digital beamforming architectures offer significantly lower overhead compared to analog and hybrid beamforming under equivalent power budgets.Comment: Submitted to IEEE Transactions for Wireless Communication

    Multi-gigabit CMOS analog-to-digital converter and mixed-signal demodulator for low-power millimeter-wave communication systems

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    The objective of the research is to develop high-speed ADCs and mixed-signal demodulator for multi-gigabit communication systems using millimeter-wave frequency bands in standard CMOS technology. With rapid advancements in semiconductor technologies, mobile communication devices have become more versatile, portable, and inexpensive over the last few decades. However, plagued by the short lifetime of batteries, low power consumption has become an extremely important specification in developing mobile communication devices. The ever-expanding demand of consumers to access and share information ubiquitously at faster speeds requires higher throughputs, increased signal-processing functionalities at lower power and lower costs. In today’s technology, high-speed signal processing and data converters are incorporated in almost all modern multi-gigabit communication systems. They are key enabling technologies for scalable digital design and implementation of baseband signal processors. Ultimately, the merits of a high performance mixed-signal receiver, such as data rate, sensitivity, signal dynamic range, bit-error rate, and power consumption, are directly related to the quality of the embedded ADCs. Therefore, this dissertation focuses on the analysis and design of high-speed ADCs and a novel broadband mixed-signal demodulator with a fully-integrated DSP composed of low-cost CMOS circuitry. The proposed system features a novel dual-mode solution to demodulate multi-gigabit BPSK and ASK signals. This approach reduces the resolution requirement of high-speed ADCs, while dramatically reducing its power consumption for multi-gigabit wireless communication systems.PhDGee-Kung Chang - Committee Chair; Chang-Ho Lee - Committee Member; Geoffrey Ye Li - Committee Member; Paul A. Kohl - Committee Member; Shyh-Chiang Shen - Committee Membe
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