Анализ тестопригодности цифровых схем на уровне регистровых передач

Запропоновано метод аналізу тестопридатності цифрових схем для детермінованого тестування більш адекватний порівняно з відомими класичними методами. Він орієнтований на комбінаційні та послідовностні схеми і базується на топологічному аналізі їх представлення на вентильному рівні та RTL. Отримані показники дозволяють легко модифікувати схему для мінімізації числа несправностей.It is proposed more suitable method of the testability analysis of the digital systems in comparison with known classical algorithmic and probabilistic methods. It is oriented on the complex combinational and sequential asynchronous logic circuits. Estimation of the testability is based on the topological analysis of the circuit. The new method and above mentioned methods were approved on the circuits of different complexity, including circuits from ISCAS’85, ‘89 Libraries. Proposed method can be used on gate-level and RT-level circuit description

High level behavioural modelling of boundary scan architecture.

This project involves the development of a software tool which enables the integration of the IEEE 1149.1/JTAG Boundary Scan Test Architecture automatically into an ASIC (Application Specific Integrated Circuit) design. The tool requires the original design (the ASIC) to be described in VHDL-IEEE 1076 Hardware Description Language. The tool consists of the two major elements: i) A parsing and insertion algorithm developed and implemented in 'C'; ii) A high level model of the Boundary Scan Test Architecture implemented in 'VHDL'. The parsing and insertion algorithm is developed to deal with identifying the design Input/Output (I/O) terminals, their types and the order they appear in the ASIC design. It then attaches suitable Boundary Scan Cells to each I/O, except power and ground and inserts the high level models of the full Boundary Scan Architecture into the ASIC without altering the design core structure