Digital signature generator for mixed-signal testing

Ponència presentada al 14th IEEE European Test SymposiumEs presenta un nou generador de signatures digitals per controlar dues senyals anàlogues. Es presenta la tecnologia STM 65 nm per demostrar la viabilitat de la proposta.Postprint (published version

Testing a Quantum Computer

The problem of quantum test is formally addressed. The presented method attempts the quantum role of classical test generation and test set reduction methods known from standard binary and analog circuits. QuFault, the authors software package generates test plans for arbitrary quantum circuits using the very efficient simulator QuIDDPro[1]. The quantum fault table is introduced and mathematically formalized, and the test generation method explained.Comment: 15 pages, 17 equations, 27 tables, 8 figure

Analog circuit test based on a digital signature

Production verification of analog circuit specifica- tions is a challenging task requiring expensive test equipment and time consuming procedures. This paper presents a method for low cost on-chip parameter verification based on the analysis of a digital signature. A 65 nm CMOS on-chip monitor is proposed and validated in practice. The monitor composes two signals (x(t), y(t)) and divides the X-Y plane with nonlinear boundaries in order to generate a digital code for every analog (x, y) location. A digital signature is obtained using the digital code and its time duration. A metric defining a discrepancy factor is used to verify circuit parameters. The method is applied to detect possible deviations in the natural frequency of a Biquad filter. Simulated and experimental results show the possibilities of the proposal.Peer ReviewedPostprint (published version

Verifying analog circuits based on a digital signature

Verification of analog circuit specifications is a challenging task requiring expensive test equipment and time consuming procedures. This paper presents a method for low cost parameter verification based on statistical analysis of a digital signature. A CMOS on-chip monitor and sampler circuit generates the digital signature of the CUT. The monitor composes two signals (x(t); y(t)) and divides the X-Y plane with nonlinear boundaries in order to generate a digital code for every analog (x; y) location. A metric to be used to discriminate the golden and defective signatures is also proposed. The metric is based on the definition of a discrepancy factor performing circuit parameter identification via statistical and pre-training procedures. The proposed method is applied to verify possible deviations on the natural frequency of a Biquad filter. Simulation results show the possibilities of the proposal.Postprint (published version

Testing a Quantum Computer

We address the problem of quantum test set generation using measurement from a single basis and the single fault model. Experimental physicists currently test quantum circuits exhaustively, meaning that each n-bit permutative circuit requires ζ x 2n tests to assure functionality, and for an m stage permutative circuit proven not to function properly the current method requires ζ x 2n x m tests as the upper bound for fault localization, where zeta varies with physical implementation. Indeed, the exhaustive methods complexity grows exponentially with the number of qubits, proportionally to the number of stages in a quantum circuit and directly with zeta. This testability bound grows still exponentially with the attempted verification of quantum effects, such as the emission of a quantum source. The exhaustive method will soon not be feasible for practical application provided the number of qubits increases even a small number from the current state of the art. An algorithm is presented making fault detection feasible both now and in the foreseeable future for quantum circuits. The presented method attempts the quantum role of classical test generation and test set reduction methods known from standard binary and analog circuits. The quantum fault table is introduced, and the test generation method explained, we show that all faults can be detected that impact calculations from the computational basis. It is believed that this fundamental research will lead to the simplification of testing for commercial quantum computers

Design, Fabrication and Veri cation of a Mixed-Signal XY Zone Monitoring Circuit and its Application to a Phase Lock Loop Circuit

El presente proyecto de final de carrera se centra en el diseño, análisis e implementación en silicio de una metodología de test/diagnosis basada en la comparación de firmas digitales generadas a partir de curvas de Lissajous. Se muestra su aplicación para testar la etapa de filtro de un circuito de bucle de enganche de fase (phase lock loop, PLL), así como los resultados experimentales de su implementación en tecnología CMOS de 65 nm. La obtención de las firmas digitales se consigue mediante el uso de un circuito monitor, el cual, a partir de la composición de dos señales periódicas del circuito a analizar, genera, para cada punto de la curva de Lissajous, un valor digital. La utilización de varios monitores con gurados de la manera adecuada permite una completa teselación del plano en diferentes zonas y por tanto, la generación de distintos códigos digitales (firma) a medida que la curva de Lissajous evoluciona en el tiempo. El test del circuito y/o diagnosis del posible defecto se realiza mediante la comparación de la signatura golden o sin defecto y la signatura generada por el circuito testado. Para la comparación de firmas se emplea el concepto de distancia de Hamming entre códigos a modo de métrica de discrepancia. A partir de los valores precalculados de la métrica para cada posible valor del defecto se consigue realizar la diagnosis de este para el parámetro en estudio. El trabajo se enmarca en el diseño de circuitos integrados de muy alta escala de integración usando una tecnología CMOS de actualidad (65 nm). Es por ello que se requieren técnicas de diseño analógico específicas, como lo son las estrategias centroidales para la elaboración de layouts o el correcto modelado de transistores nanométricos. Para esto último se hace uso del modelo Berkeley, el cual, debidamente ajustado a la tecnología empleada, proporciona aproximaciones muy aceptables y con relativa facilidad de uso. Con el objetivo de verificar la metodología de test/diagnosis propuesta, se hace uso de una aplicación Matlab que permite simular el comportamiento del circuito a testar en diferentes situaciones. Es posible excitar el circuito con distintas entradas, cambiar los parámetros de este, introducir defectos, o emplear distintos conjuntos de curvas para teselar el plano. La aplicación resulta fundamental para efectuar el proceso de diagnosis pues relaciona la cantidad de defecto con los valores de discrepancia obtenidos con la métrica definida. Finalmente, se presentan los resultados experimentales obtenidos con el chip fabricado. Se constata el correcto comportamiento de este y la validez de la metodología de test/diagnosis propuesta