1,070 research outputs found
Metastability-Containing Circuits
In digital circuits, metastability can cause deteriorated signals that
neither are logical 0 or logical 1, breaking the abstraction of Boolean logic.
Unfortunately, any way of reading a signal from an unsynchronized clock domain
or performing an analog-to-digital conversion incurs the risk of a metastable
upset; no digital circuit can deterministically avoid, resolve, or detect
metastability (Marino, 1981). Synchronizers, the only traditional
countermeasure, exponentially decrease the odds of maintained metastability
over time. Trading synchronization delay for an increased probability to
resolve metastability to logical 0 or 1, they do not guarantee success.
We propose a fundamentally different approach: It is possible to contain
metastability by fine-grained logical masking so that it cannot infect the
entire circuit. This technique guarantees a limited degree of metastability
in---and uncertainty about---the output.
At the heart of our approach lies a time- and value-discrete model for
metastability in synchronous clocked digital circuits. Metastability is
propagated in a worst-case fashion, allowing to derive deterministic
guarantees, without and unlike synchronizers. The proposed model permits
positive results and passes the test of reproducing Marino's impossibility
results. We fully classify which functions can be computed by circuits with
standard registers. Regarding masking registers, we show that they become
computationally strictly more powerful with each clock cycle, resulting in a
non-trivial hierarchy of computable functions
Delay Flip-Flop (DFF) Metastability Impact on Clock and Data Recovery (CDR) and Phase-Locked Loop (PLL) Circuits
Modeling delay flip-flops for binary (e.g., Alexander) phase detectors requires paying close attention to three important timing parameters: setup time, hold time, and clock edge-to-output (or briefly C2Q time). These parameters have a critical role in determining the status of the system on the circuit level. This study provided a guideline for designing an optimum DFF for an Alexander phase detector in a clock and data recovery circuit. Furthermore, it indicated DFF timing requirements for a high-speed phase detector in a clock and data recovery circuit. The CDR was also modeled by Verilog-A, and the results were compared with Simulink model achievements. Eventually designed in 45 nm CMOS technology, for 10 Gbps random sequence, the recovered clock contained 0.136 UI and 0.15 UI peak-to-peak jitter on the falling and rising edges respectively, and the lock time was 125 ns. The overall power dissipation was 21 mW from a 1 V supply voltage. Future work includes layout design and manufacturing of the proposed design
Effect of Jitter on the Settling Time of Mesochronous Clock Retiming Circuits
It is well known that timing jitter can degrade the bit error rate (BER) of
receivers that recover the clock from input data. However, timing jitter can
also result in an indefinite increase in the settling time of clock recovery
circuits, particularly in low swing mesochronous systems. Mesochronous clock
retiming circuits are required in repeaterless low swing on-chip interconnects.
We first discuss how timing jitter can result in a large increase in the
settling time of the clock recovery circuit. Next, the circuit is modelled as a
Markov chain with absorbing states. The mean time to absorption of the Markov
chain, which represents the mean settling time of the circuit, is determined.
The model is validated through behavioural simulations of the circuit, the
results of which match well with the model predictions. We consider circuits
with (i) data dependent jitter, (ii) random jitter, and (iii) combination of
both of them. We show that a mismatch between the strengths of up and down
corrections of the retiming can reduce the settling time. In particular, a 10%
mismatch can reduce the mean settling time by up to 40%. We leverage this fact
toward improving the settling time performance, and propose useful techniques
based on biased training sequences and mismatched charge pumps. We also present
a coarse+fine clock retiming circuit, which can operate in coarse first mode,
to reduce the settling time substantially. These fast settling retiming
circuits are verified with circuit simulations.Comment: 23 pages, 40 figure
PieceTimer: A Holistic Timing Analysis Framework Considering Setup/Hold Time Interdependency Using A Piecewise Model
In static timing analysis, clock-to-q delays of flip-flops are considered as
constants. Setup times and hold times are characterized separately and also
used as constants. The characterized delays, setup times and hold times, are
ap- plied in timing analysis independently to verify the perfor- mance of
circuits. In reality, however, clock-to-q delays of flip-flops depend on both
setup and hold times. Instead of being constants, these delays change with
respect to different setup/hold time combinations. Consequently, the simple ab-
straction of setup/hold times and constant clock-to-q delays introduces
inaccuracy in timing analysis. In this paper, we propose a holistic method to
consider the relation between clock-to-q delays and setup/hold time
combinations with a piecewise linear model. The result is more accurate than
that of traditional timing analysis, and the incorporation of the
interdependency between clock-to-q delays, setup times and hold times may also
improve circuit performance.Comment: IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
November 201
Delay Measurements and Self Characterisation on FPGAs
This thesis examines new timing measurement methods for self delay characterisation of Field-Programmable Gate Arrays (FPGAs) components and delay measurement of complex circuits
on FPGAs. Two novel measurement techniques based on analysis of a circuit's output failure
rate and transition probability is proposed for accurate, precise and efficient measurement of
propagation delays. The transition probability based method is especially attractive, since
it requires no modifications in the circuit-under-test and requires little hardware resources,
making it an ideal method for physical delay analysis of FPGA circuits.
The relentless advancements in process technology has led to smaller and denser transistors
in integrated circuits. While FPGA users benefit from this in terms of increased hardware
resources for more complex designs, the actual productivity with FPGA in terms of timing
performance (operating frequency, latency and throughput) has lagged behind the potential
improvements from the improved technology due to delay variability in FPGA components
and the inaccuracy of timing models used in FPGA timing analysis. The ability to measure
delay of any arbitrary circuit on FPGA offers many opportunities for on-chip characterisation
and physical timing analysis, allowing delay variability to be accurately tracked and variation-aware optimisations to be developed, reducing the productivity gap observed in today's FPGA
designs.
The measurement techniques are developed into complete self measurement and characterisation platforms in this thesis, demonstrating their practical uses in actual FPGA hardware for
cross-chip delay characterisation and accurate delay measurement of both complex combinatorial and sequential circuits, further reinforcing their positions in solving the delay variability
problem in FPGAs
RTL Design Quality Checks for Soft IPs
Soft IPs are architectural modules which are delivered in the form of synthesizable RTL level codes written in some HDL (hardware descriptive language) like Verilog or VHDL or System Verilog. They are technology independent and offer high degree of modification flexibility. RTL is the complete abstraction of our design. Since SOC complexity is growing day by day with new technologies and requirement, it will be very much difficult to debug and fix issues after physical level. So to reduce effort and increase efficiency and accuracy it is necessary to fix most of the bugs in RTL level. Also if we are using soft IP, then our bug free IP can be used by third party. So early detection of bugs helps us not to go back to entire design and do all the process again and again. One of the important issue at RTL level of a design is the Clock Domain Crossing (CDC) problem. This is the issue which affects the performance at each and every stage of the design flow. Failure in fixing these issues at the earlier stage makes the design unreliable and design performance collapses. The main issue in real time clock designs are the metastability issue. Although we cannot check or see these issues using our simulator but we have to make preventions at RTL level. This is done by restructuring the design and adding required synchronizers. One more important area of consideration in VLSI design is power consumption. In modern low power designs low power is a key factor. So design consuming less power is preferred over design consuming more power. This decision should be made as early as possible. RTL quality check helps us on this aspect. Using different tools power estimation can be performed at RTL stage which saves lots of efforts in redesigning. This project aims at checking clock domain crossing faults at RTL stage and doing redesign of circuit to eliminate those faults. Also an effort is made to compare quality of two designs in terms of delay, power consumption and area
Synchronizer-Free Digital Link Controller
This work presents a producer-consumer link between two independent clock
domains. The link allows for metastability-free, low-latency, high-throughput
communication by slight adjustments to the clock frequencies of the producer
and consumer domains steered by a controller circuit. Any such controller
cannot deterministically avoid, detect, nor resolve metastability. Typically,
this is addressed by synchronizers, incurring a larger dead time in the control
loop. We follow the approach of Friedrichs et al. (TC 2018) who proposed
metastability-containing circuits. The result is a simple control circuit that
may become metastable, yet deterministically avoids buffer underrun or
overflow. More specifically, the controller output may become metastable, but
this may only affect oscillator speeds within specific bounds. In contrast,
communication is guaranteed to remain metastability-free. We formally prove
correctness of the producer-consumer link and a possible implementation that
has only small overhead. With SPICE simulations of the proposed implementation
we further substantiate our claims. The simulation uses 65nm process running at
roughly 2GHz.Comment: 12 page journal articl
Perspectives on the Neuroscience of Cognition and Consciousness
The origin and current use of the concepts of computation, representation and information in Neuroscience are examined and conceptual flaws are identified which vitiate their usefulness for addressing problems of the neural basis of Cognition and Consciousness. In contrast, a convergence of views is presented to support the characterization of the Nervous System as a complex dynamical system operating in the metastable regime, and capable of evolving to configurations and transitions in phase space with potential relevance for Cognition and Consciousness
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