3,348 research outputs found
Optimizing Scrubbing by Netlist Analysis for FPGA Configuration Bit Classification and Floorplanning
Existing scrubbing techniques for SEU mitigation on FPGAs do not guarantee an
error-free operation after SEU recovering if the affected configuration bits do
belong to feedback loops of the implemented circuits. In this paper, we a)
provide a netlist-based circuit analysis technique to distinguish so-called
critical configuration bits from essential bits in order to identify
configuration bits which will need also state-restoring actions after a
recovered SEU and which not. Furthermore, b) an alternative classification
approach using fault injection is developed in order to compare both
classification techniques. Moreover, c) we will propose a floorplanning
approach for reducing the effective number of scrubbed frames and d),
experimental results will give evidence that our optimization methodology not
only allows to detect errors earlier but also to minimize the
Mean-Time-To-Repair (MTTR) of a circuit considerably. In particular, we show
that by using our approach, the MTTR for datapath-intensive circuits can be
reduced by up to 48.5% in comparison to standard approaches
General purpose readout board {\pi} LUP: overview and results
This work gives an overview of the PCI-Express board LUP, focusing on
the motivation that led to its development, the technological choices adopted
and its performance. The LUP card was designed by INFN and University of
Bologna as a readout interface candidate to be used after the Phase-II upgrade
of the Pixel Detector of the ATLAS and CMS experiments at LHC. The same team in
Bologna is also responsible for the design and commissioning of the ReadOut
Driver (ROD) board - currently implemented in all the four layers of the ATLAS
Pixel Detector (Insertable B-Layer, B-Layer, Layer-1 and Layer-2) - and
acquired in the past years expertise on the ATLAS readout chain and the
problematics arising in such experiments. Although the LUP was designed to
fulfill a specific task, it is highly versatile and might fit a wide variety of
applications, some of which will be discussed in this work. Two
7-generation Xilinx FPGAs are mounted on the board: a Zynq-7 with an
embedded dual core ARM Processor and a Kintex-7. The latter features sixteen
12.5Gbps transceivers, allowing the board to interface easily to any other
electronic board, either electrically and/or optically, at the current
bandwidth of the experiments for LHC. Many data-transmission protocols have
been tested at different speeds, results will be discussed later in this work.
Two batches of LUP boards have been fabricated and tested, two boards in
the first batch (version 1.0) and four boards in the second batch (version
1.1), encapsulating all the patches and improvements required by the first
version.Comment: 6 pages, 10 figures, 21th Real Time Conference, winner of "2018 NPSS
Student Paper Award Second Prize
LEGaTO: first steps towards energy-efficient toolset for heterogeneous computing
LEGaTO is a three-year EU H2020 project which started in December 2017. The LEGaTO project will leverage task-based programming models to provide a software ecosystem for Made-in-Europe heterogeneous hardware composed of CPUs, GPUs, FPGAs and dataflow engines. The aim is to attain one order of magnitude energy savings from the edge to the converged cloud/HPC.Peer ReviewedPostprint (author's final draft
- …