An efficient logic fault diagnosis framework based on effect-cause approach

Fault diagnosis plays an important role in improving the circuit design process and the manufacturing yield. With the increasing number of gates in modern circuits, determining the source of failure in a defective circuit is becoming more and more challenging. In this research, we present an efficient effect-cause diagnosis framework for combinational VLSI circuits. The framework consists of three stages to obtain an accurate and reasonably precise diagnosis. First, an improved critical path tracing algorithm is proposed to identify an initial suspect list by backtracing from faulty primary outputs toward primary inputs. Compared to the traditional critical path tracing approach, our algorithm is faster and exact. Second, a novel probabilistic ranking model is applied to rank the suspects so that the most suspicious one will be ranked at or near the top. Several fast filtering methods are used to prune unrelated suspects. Finally, to refine the diagnosis, fault simulation is performed on the top suspect nets using several common fault models. The difference between the observed faulty behavior and the simulated behavior is used to rank each suspect. Experimental results on ISCAS85 benchmark circuits show that this diagnosis approach is efficient both in terms of memory space and CPU time and the diagnosis results are accurate and reasonably precise

Evaluation of backtracing based diagnosis algorithms

With the growing size and complexity of modern circuits, more algorithms are being developed nowadays for efficient fault diagnosis. Backtracing based diagnosis algorithms are effect-cause approaches that start from the failing outputs of the circuit and try to diagnose fault locations by backtracing lines toward the circuit inputs. In this thesis, general functionality was extracted between backtracing based diagnosis algorithms and implemented as an extension to an existing diagnosis framework. Furthermore, a simple graphical user interface was developed for the extended framework. The extended framework aims at facilitating the implementation and evaluation of different backtracing based diagnosis algorithms. In order to demonstrate its powerfulness, two modern backtracing based diagnosis algorithms were implemented on top of the extended framework. A number of diagnosis experiments on benchmark circuits was carried out in order to evaluate the two implemented algorithms. The experimental tools used and the results obtained are presented

An Improved Method of Per-Test X-Fault Diagnosis for Deep-Submicron LSI Circuits

Per-test diagnosis based on the X-fault model is an effective approach for a circuit with physical defects of nondeterministic logic behavior. However, the extensive use of vias and the unpredictable order relation among threshold voltages at fanout branches, both being typical phenomena in a deep-submicron circuit, have not been fully addressed by conventional per-test X-fault diagnosis. To solve these problems, this paper proposes an improved per-test X-fault diagnosis method, featuring (1) an extended X-fault model to handle vias and (2) occurrence probabilities of logic behavior for a physical defect to handle the unpredictable relation among threshold voltages. Experimental result show the effectiveness of the proposed method.7th Workshop on RTL and High Level Testing (WRTLT`06), November 23-24, 2006, Fukuoka, Japa

Machine learning methods for fault classification

With the constant evolution and ever-increasing transistor densities in semiconductor technology, error rates are on the rise. Errors that occur on semiconductor chips can be attributed to permanent, transient or intermittent faults. Out of these errors, once permanent errors appear, they do not go away and once intermittent faults appear on chips, the probability that they will occur again is high, making these two types of faults critical. Transient faults occur very rarely, making them non-critical. Incorrect classification during manufacturing tests in case of critical faults, may result in failure of the chip during operational lifetime or decrease in product quality, whereas discarding chips with non-critical faults may result in unnecessary yield loss. Existing mechanisms to distinguish between the fault types are mostly rule-based, and as fault types start manifesting similarly as we move to lower technology nodes, these rules become obsolete over time. Hence, rules need to be updated every time the technology is changed. Machine learning approaches have shown that the uncertainty can be compensated with previous experience. In our case, the ambiguity of classification rules can be compensated by storing past classification decisions and learn from those for accurate classification. This thesis presents an effective solution to the problem of fault classification in VLSI chips using Support Vector Machine (SVM) based machine learning techniques

Test and Diagnosis of Integrated Circuits

The ever-increasing growth of the semiconductor market results in an increasing complexity of digital circuits. Smaller, faster, cheaper and low-power consumption are the main challenges in semiconductor industry. The reduction of transistor size and the latest packaging technology (i.e., System-On-a-Chip, System-In-Package, Trough Silicon Via 3D Integrated Circuits) allows the semiconductor industry to satisfy the latest challenges. Although producing such advanced circuits can benefit users, the manufacturing process is becoming finer and denser, making chips more prone to defects.The work presented in the HDR manuscript addresses the challenges of test and diagnosis of integrated circuits. It covers:- Power aware test;- Test of Low Power Devices;- Fault Diagnosis of digital circuits

Proceedings of the 22nd Conference on Formal Methods in Computer-Aided Design – FMCAD 2022

The Conference on Formal Methods in Computer-Aided Design (FMCAD) is an annual conference on the theory and applications of formal methods in hardware and system verification. FMCAD provides a leading forum to researchers in academia and industry for presenting and discussing groundbreaking methods, technologies, theoretical results, and tools for reasoning formally about computing systems. FMCAD covers formal aspects of computer-aided system design including verification, specification, synthesis, and testing

Proceedings of the 22nd Conference on Formal Methods in Computer-Aided Design – FMCAD 2022

The Conference on Formal Methods in Computer-Aided Design (FMCAD) is an annual conference on the theory and applications of formal methods in hardware and system verification. FMCAD provides a leading forum to researchers in academia and industry for presenting and discussing groundbreaking methods, technologies, theoretical results, and tools for reasoning formally about computing systems. FMCAD covers formal aspects of computer-aided system design including verification, specification, synthesis, and testing

Fehlercharakterisierung zuverlässiger Schaltungen im Selbsttest

Hochintegrierte Schaltungen können immer kleiner, höher getaktet und energieeffizienter hergestellt werden, allerdings können bedingt durch diese technologischen Trends auch vermehrt Schwachstellen im System entstehen. Diese Schwachstellen führen oft während des Produktionstests nicht zu einem Fehlverhalten der Schaltung, während des Betriebs allerdings droht durch die steigende Anfälligkeit gegenüber intrinsischen und äußeren Störeinflüssen sowie Alterungseffekten ein vorzeitiger Ausfall der Schaltung. Solche Frühausfälle werden „Early-Life Fehler“ genannt und können mit einem Standard- Test ohne weitere Anpassungen nicht erkannt werden. Indikatoren für einen Frühausfall können intermittierende Fehler, aber auch kleine Verzögerungsfehler sein. In dieser Arbeit wird ein Selbsttest vorgestellt, der eine Fehlercharakterisierung zur Erkennung von Systemschwachstellen und Vermeidung von Frühausfällen, speziell solche, die sich als intermittierender Fehler oder kleiner Verzögerungsfehler auswirken, mit geringem Hardware- und Zeitaufwand mittels eines Standard-Tests ermöglicht. Hierzu wird im Selbsttest zunächst zwischen permanenten und nicht-permanenten Fehlern unterschieden und eine Klassifikation der nicht- permanenten Fehler mit Hilfe eines voran geschalteten Diagnoseverfahrens und Bayesschen Berechnungen durchgeführt. Hierdurch lässt sich die Produktqualität ohne zusätzliche Ausbeuteverluste erhöhen. Zusätzlich wird ein Test mit erhöhter Betriebsfrequenz vorgestellt, der im Selbsttest kleine Verzögerungsfehler erkennt.As a result of the fact, that todays integrated circuits have smaller features sizes, higher frequencies and are more energy efficient, weak spots can occur in the system. These weak spots can be undetected by the production test, but during system operation they can lead to hard failures, because of increasing susceptibility to intrinsic and external disturbances or aging effects. This early system breakdown is called „early-life failure“ and cannot be detected by a standard test without any adjustments. Indicators of early-life failures could be intermittent faults and also small delay defects. In this thesis a built-in self-test is presented, which characterizes faulty behavior to detect weak spots and avoid early-life failures, especially caused by intermittent faults or small delay defects, with low hardware and time overhead by using a standard test set. In a first step, the test procedure can distinguish between permanent and non-permanent faults. After that, a diagnosis process and Bayesian reasoning implement the classification of the non-permanent faults. With this procedure the product quality can be increased without additional yield loss. Furthermore a Faster-than-at-Speed-Test (FAST) will be introduced, which allows detecting SDDs in a built-in self-test environment without any changes in the ATPG flow.von Dipl.-Wirt.-Ing. Thomas Indlekofer ; Erster Gutachter: Prof. Dr. Sybille Hellebrand, Zweiter Gutachter: Prof. Dr. Ilia PolianTag der Verteidigung: 03.03.2016Fakultät für Elektrotechnik, Informatik und Mathematik der Universität Paderborn, Univ., Dissertation, 201

A knowledge based structure for implementing Value Management in the design of office buildings

Value Management (VM) is an organised effort directed at analyzing the functionsof systems, supplies, equipments and facilities, for the purpose of achieving therequired functions at lowest overall cost, consistent with requirements for performance,including reliability, delivery, maintainability and human factors. Thisstructured method can also be successfully used to define the scope of a project. Inthe UK, the awareness of the tremendous potential and benefits of applying VM toconstruction projects has made some clients eager to apply this technique to theirprojects. There are, however, a number of problems which inhibit the use of thisadvanced technique in the construction industry. Qualified VM specialists, forinstance, are very scarce within the industry, it is often difficult to find them toundertake proper VM studies. This research therefore aimed at exploring thefeasibility of building a Knowledge-Based System (KBS) to facilitate VM implementationsin the design stages of a construction project. A demonstration system has beensuccessfully developed to illustrate the facilities which would be available to potentialusers in a fully developed system. A method of allocating project cost againstfunctions of the project specified by the clients has been developed, which couldexpedite the processes of clarifying clients' brief and ensuring good value for moneyby cutting unnecessary costs and enhancing required functions. The research has alsoexplored how KBSs can be effectively applied to "open-ended" decision-makingproblems in which new options may be generated during each session with thesystem, i.e. the study considered the possibility of letting users extend and customisethe knowledge base. The system has been described as a "satisfactory and verypromising system" by the UK industrial specialists