Design of a tunable multi-band differential LC VCO using 0.35 mu m SiGe BiCMOS technology for multi-standard wireless communication systems

In this paper, an integrated 2.2-5.7GHz multi-band differential LC VCO for multi-standard wireless communication systems was designed utilizing 0.35 mu m SiGe BiCMOS technology. The topology, which combines the switching inductors and capacitors together in the same circuit, is a novel approach for wideband VCOs. Based on the post-layout simulation results, the VCO can be tuned using a DC voltage of 0 to 3.3 V for 5 different frequency bands (2.27-2.51 GHz, 2.48-2.78 GHz, 3.22-3.53 GHz, 3.48-3.91 GHz and 4.528-5.7 GHz) with a maximum bandwidth of 1.36 GHz and a minimum bandwidth of 300 MHz. The designed and simulated VCO can generate a differential output power between 0.992 and -6.087 dBm with an average power consumption of 44.21 mW including the buffers. The average second and third harmonics level were obtained as -37.21 and -47.6 dBm, respectively. The phase noise between -110.45 and -122.5 dBc/Hz, that was simulated at 1 MHz offset, can be obtained through the frequency of interest. Additionally, the figure of merit (FOM), that includes all important parameters such as the phase noise, the power consumption and the ratio of the operating frequency to the offset frequency, is between -176.48 and -181.16 and comparable or better than the ones with the other current VCOs. The main advantage of this study in comparison with the other VCOs, is covering 5 frequency bands starting from 2.27 up to 5.76 GHz without FOM and area abandonment. Output power of the fundamental frequency changes between -6.087 and 0.992 dBm, depending on the bias conditions (operating bands). Based on the post-layout simulation results, the core VCO circuit draws a current between 2.4-6.3 mA and between 11.4 and 15.3 mA with the buffer circuit from 3.3 V supply. The circuit occupies an area of 1.477 mm(2) on Si substrate, including DC, digital and RF pads

Realization of a voltage controlled oscillator using 0.35 um sige-bicmos technology for multi-band applications

The stable growth in wireless communications market has engendered the interoperability of various standards in a single broadband frequency range from hundred MHz up to several GHz. This frequency range consists of various wireless applications such as GSM, Bluetooth and WLAN. Therefore, an agile wireless system needs smart RF front-ends for functioning properly in such a crowded spectrum. As a result, the demand for multi-standard RF transceivers which put various wireless and cordless phone standards together in one structure was increased. The demand for multi-standard RF transceivers gives a key role to reconfigurable wideband VCO operation with low-power and low-phase noise characteristics. Besides agility and intelligence, such a communication system (GSM, WLAN, Global Positioning Systems, etc. ) required meeting the requirements of several standards in a cost-effective way. This, when cost and integration are the major concerns, leads to the exploitation of Si-based technologies. In this thesis, an integrated 2.2-5.7GHz Multi-band differential LC VCO for Multi-standard Wireless Communication systems was designed utilizing 0.35μm SiGe BiCMOS technology. The topology, which combines the switching inductors and capacitors together in the same circuit, is a novel approach for wideband VCOs. Based on the post layout simulation results, the VCO can be tuned using a DC voltage of 0 to 3.3V for 5 different frequency bands (2.27-2.51 GHz, 2.48-2.78GHz, 3.22-3.53GHz, 3.48-3.91GHz and 4.528-5.7GHz) with a maximum bandwidth of 1.36GHz and a minimum bandwidth of 300MHz. The designed and simulated VCO can generate a differential output power between 0.992 dBm and -6.087 dBm with an average power consumption of 44.21mW including the buffers. The average second and third harmonics level were obtained as -37.21 dBm and -47.6 dBm, respectively. The phase noise between -110.45 and -122.5 dBc/Hz, that was simulated at 1 MHz offset, can be obtained through the frequency of interest. Additionally, the figure of merit (FOM), that includes all important parameters such as the phase noise, the power consumption and the ratio of the operating frequency to the offset frequency, is between -176.48 and -181.16 and comparable or better than the ones with the other current VCOs. The main advantage of this study in comparison with the other VCOs, is covering 5 frequency bands starting from 2.27 up to 5.76 GHz without FOM and area abandonment

Theory Based on Device Current Clipping to Explain and Predict Performance Including Distortion of Power Amplifiers for Wireless Communication Systems

Power amplifiers are critical components in wireless communication systems that need to have high efficiency, in order to conserve battery life and minimise heat generation, and at the same time low distortion, in order to prevent increase of bit error rate due to constellation errors and adjacent channel interference. This thesis is aimed at meeting a need for greater understanding of distortion generated by power amplifiers of any technology, in order to help designers manage better the trade-off between obtaining high efficiency and low distortion. The theory proposed in this thesis to explain and predict the performance of power amplifiers, including distortion, is based on analysis of clipping of the power amplifier device current, and it is a major extension of previous clipping analyses, that introduces many key definitions and concepts. Distortion and other power amplifier metrics are determined in the form of 3-D surfaces that are plotted against PA class, which is determined by bias voltage, and input signal power level. It is shown that the surface of distortion exhibits very high levels due to clipping in the region where efficiency is high. This area of high distortion is intersected by a valley that is ‘L’-shaped. The 'L'-shaped valley is subject to a rotation that depends on the softness of the cut-off of the power amplifier device transfer characteristic. The distortion surface with rotated 'L'-shaped valley leads to predicted curves for distortion versus input signal power that match published measured curves for power amplifiers even using very simple device models. The distortion versus input signal power curves have types that are independent of technology. In class C, there is a single deep null. In the class AB range, that is divided into three sub-ranges, there may be two deep nulls (sub-range AB(B)), a ledge (sub-range AB(A)) or a shallow null with varying depth (sub-range AB(AB))

SiGe based multiple-phase VCO operating for mm-wave frequencies

The ever-increasing demand for higher speed in wireless consumer applications has increased the interest in the unlicensed spectrum of 7 GHz around 60 GHz. The high atmospheric oxygen absorption at 60 GHz and small size of the antennas at this frequency requires the use of integrated phased-array systems to overcome the deficiencies of lossy channels at these frequencies. The phased arrays combine signals from multiple paths to obtain higher receiver sensitivity and directivity. The system thus requires phase-shifted voltage-controlled oscillator (VCO) signals to implement phase shifting in the local-oscillator (LO) path. In this research, the vector sum method to generate various phases of the signal at 60 GHz was investigated for its suitability in phased-array systems. The main focus was on improving the phase noise performance of the VCO. The VCO was implemented using a fully differential common-collector Colpitts oscillator in the cascode configuration, which was found to be the VCO configuration with acceptable phase noise performance and stability in the millimetre-wave range. The research focus was on modelling the phase noise of the VCO, and was performed by identifying the impulse sensitivity function for various noise sources, followed by analysing its effect on the linear time varying (LTV) model of the oscillators. The analysis led to a closed-form expression for the phase noise of the oscillator in terms of process and design parameters. The design was then optimised in terms of identified parameters to attain minimum phase noise. The phase noise expression using LTV theory and SpectreRF simulations reported the same optimum value for the design parameter, of around 0.3 for the capacitor ratio. The simulation results utilising the vector sum phase shifting method to generate multiple phase oscillator signals suggest its suitability in implementing phased-array systems in the millimetre-wave range. The vector sum was realised by generating quadrature signals from the oscillator using hybrid couplers. Variable gain amplifiers (VGAs) based on Gilbert mixer topology were used to combine the in-phase and quadrature phase signals to generate the phase-shifted oscillator signal. The gains of the VGAs were linearised by using a pre-distortion circuit, which was an inverse tanh cell. A fully differential 60 GHz VCO was fabricated using a SiGe process with a fT of 200 GHz. The fabricated integrated circuit (IC) measured at the wafer level had a centre frequency of 52.8 GHz and a tuning range of 7 GHz. It demonstrated a phase noise performance of -98.9 dBc/Hz at 1 MHz offset and a power dissipation of 140 mW, thus providing a VCO figure of merit of 172 dBc/Hz. It delivered a differential output power of 8 dBm and the IC occupied an area of 0.54 mm2, including the bondpads. It was thus concluded that a 10 % design margin for the tuning range is required while using SiGe BiCMOS technology. The simulation results demonstrate that the VCO, along with an active interpolator, provides a range of phase-shifted signals from 0° to 360° in steps of 22.5° for various gain settings of the VGAs. The power dissipation of the active interpolator is around 60 mW and the system could thus be employed in LO path shifting architecture of the phased arrays with increased power consumption.Thesis (PhD)--University of Pretoria, 2013.Electrical, Electronic and Computer Engineeringunrestricte

On-chip Electro-static Discharge (esd) Protection For Radio-frequency Integrated Circuits

Electrostatic Discharge (ESD) phenomenon is a common phenomenon in daily life and it could damage the integrated circuit throughout the whole cycle of product from the manufacturing. Several ESD stress models and test methods have been used to reproduce ESD events and characterize ESD protection device\u27s performance. The basic ESD stress models are: Human Body Model (HBM), Machine Model (MM), and Charged Device Model (CDM). On-chip ESD protection devices are widely used to discharge ESD current and limit the overstress voltage under different ESD events. Some effective ESD protection devices were reported for low speed circuit applications such as analog ICs or digital ICs in CMOS process. On the contrast, only a few ESD protection devices available for radio frequency integrated circuits (RF ICs). ESD protection for RF ICs is more challenging than traditional low speed CMOS ESD protection design because of the facts that: (1) Process limitation: High-performance RF ICs are typically fabricated in compound semiconductor process such as GaAs pHEMT and SiGe HBT process. And some proved effective ESD devices (e.g. SCR) are not able to be fabricated in those processes due to process limitation. Moreover, compound semiconductor process has lower thermal conductivity which will worsen its ESD damage immunity. (2) Parasitic capacitance limitation: Even for RF CMOS process, the inherent parasitic capacitance of ESD protection devices is a big concern. Therefore, this dissertation will contribute on ESD protection designs for RF ICs in all the major processes including GaAs pHEMT, SiGe BiCMOS and standard CMOS. iv The ESD protection for RF ICs in GaAs pHEMT process is very difficult, and the typical HBM protection level is below 1-kV HBM level. The first part of our work is to analyze pHEMT\u27s snapback, post-snapback saturation and thermal failure under ESD stress using TLP-like Sentaurus TCAD simulation. The snapback is caused by virtual bipolar transistor due to large electron-hole pairs impacted near drain region. Postsnapback saturation is caused by temperature-induced mobility degradation due to IIIV compound semiconductor materials\u27 poor thermal conductivity. And thermal failure is found to be caused by hot spot located in pHEMT\u27s InGaAs layer. Understanding of these physical mechanisms is critical to design effective ESD protection device in GaAs pHEMT process. Several novel ESD protection devices were designed in 0.5um GaAs pHEMT process. The multi-gate pHEMT based ESD protection devices in both enhancementmode and depletion-mode were reported and characterized then. Due to the multiple current paths available in the multi-gate pHEMT, the new ESD protection clamp showed significantly improved ESD performances over the conventional single-gate pHEMT ESD clamp, including higher current discharge capability, lower on-state resistance, and smaller voltage transient. We proposed another further enhanced ESD protection clamp based on a novel drain-less, multi-gate pHEMT in a 0.5um GaAs pHEMT technology. Based on Barth 4002 TLP measurement results, the ESD protection devices proposed in this chapter can improve the ESD level from 1-kV (0.6 A It2) to up to 8-kV ( \u3e 5.2 A It2) under HBM. v Then we optimized SiGe-based silicon controlled rectifiers (SiGe SCR) in SiGe BiCMOS process. SiGe SCR is considered a good candidate ESD protection device in this process. But the possible slow turn-on issue under CDM ESD events is the major concern. In order to optimize the turn-on performance of SiGe SCR against CDM ESD, the Barth 4012 very fast TLP (vfTLP) and vfTLP-like TCAD simulation were used for characterization and analysis. It was demonstrated that a SiGe SCR implemented with a P PLUG layer and minimal PNP base width can supply the smallest peak voltage and fastest response time which is resulted from the fact that the impact ionization region and effective base width in the SiGe SCR were reduced due to the presence of the P PLUG layer. This work demonstrated a practical approach for designing optimum ESD protection solutions for the low-voltage/radio frequency integrated circuits in SiGe BiCMOS process. In the end, we optimized SCRs in standard silicon-based CMOS process to supply protection for high speed/radio-frequency ICs. SCR is again considered the best for its excellent current handling ability. But the parasitic capacitance of SCRs needs to be reduced to limit SCR\u27s impact to RF performance. We proposed a novel SCR-based ESD structure and characterize it experimentally for the design of effective ESD protection in high-frequency CMOS based integrated circuits. The proposed SCR-based ESD protection device showed a much lower parasitic capacitance and better ESD performance than the conventional SCR and a low-capacitance SCR reported in the literature. The physics underlying the low capacitance was explained by measurements using HP 4284 capacitance meter. vi Throughout the dissertation work, all the measurements are mainly conducted using Barth 4002 transimission line pulsing (TLP) and Barth 4012 very fast transmission line pulsing (vfTLP) testers. All the simulation was performed using Sentaurus TCAD tool from Synopsys

ADVANCED MODELING APPROACHES FOR MICROWAVE FET DEVICES & SUB-SYSTEMS

Ph.DDOCTOR OF PHILOSOPH

Conception et intégration en technologie LTCC d'un amplificateur faible bruit à structure balancée dans la bande C

Les performances des systèmes électroniques modernes pour les applications spatiales et militaires sont confrontées à de grandes attentes, notamment des densités d’intégration plus élevées et des facteurs de forme plus petits. Ce défi a généré un fort besoin de miniaturisation et d’intégration à un niveau supérieur. Par ailleurs, des performances larges bandes sont souvent recherchées en raison de l'augmentation du débit des données ou encore, dans le cas des systèmes de communications tactiques, en raison de la nature de l’application. Afin d’atteindre l’ensemble de ces objectifs, le choix d’une technologie de fabrication bien appropriée est nécessaire. La technologie LTCC (Low Temperature Co-fired Ceramic) offre la possibilité d'incorporer des composants passifs à l’intérieur du substrat ce qui permet de réduire considérable la taille d'un circuit. Entre autres, la technologie LTCC est particulièrement intéressante pour la conception de modules RF microondes et millimétriques à cause des faibles pertes qu’elle présente à ces fréquences. Ceci favorise l'efficacité énergétique pour les circuits de puissance et implique des facteurs de qualité plus élevés dans différents types de structures passives. Cependant, il faut garantir que les performances RF, d'un composant donné, soient maintenues lorsqu’il est inséré dans le substrat en ajoutant les transitions adéquates entre les différentes couches. Ce mémoire porte sur la conception et l’intégration d’un LNA (Low Noise Amplifier) large bande à structure balancée en technologie LTCC destiné aux applications tactiques. L’objectif principal est d’identifier et de valider expérimentalement les moyens de miniaturiser le circuit dans le but de réaliser un LNA centré à 4.7 GHz avec une bande passante de 600 MHz. La structure balancée est composée principalement de deux coupleurs hybrides 90° et de deux transistors RF à faible bruit. Le prototype du LNA figure parmi les premiers circuits complexes fabriqués en technologie LTCC au laboratoire LACIME de l’ÉTS. Les résultats préliminaires confirment l’intérêt de développer une seconde itération de fabrication. Ce travail de recherche propose aussi la conception et l’intégration 3D d’un coupleur hybride 90° à lignes couplées dissimulées dans le corps du substrat. Le coupleur, conçu initialement pour être intégré à la structure balancée du LNA, reste valable pour d’autres applications RF. Les transitions nécessaires à l’intégration du coupleur ont été optimisées pour une meilleure adaptation. Les résultats expérimentaux du coupleur s’accordent étroitement aux simulations et présentent de bonnes performances sur une large bande de fréquences d’opération [3.2 GHz - 5.1 GHz]; des coefficients de réflexion inférieurs à -15dB, une balance en amplitude de ±0.5 dB, un déphasage de 90°±1.5 et une taille miniaturisée (3.3 × 6.8 × 2.15 mm3). Le coupleur opère à des températures de -55°C à +85ºC

Unified Framework for Multicarrier and Multiple Access based on Generalized Frequency Division Multiplexing

The advancements in wireless communications are the key-enablers of new applications with stringent requirements in low-latency, ultra-reliability, high data rate, high mobility, and massive connectivity. Diverse types of devices, ranging from tiny sensors to vehicles, with different capabilities need to be connected under various channel conditions. Thus, modern connectivity and network techniques at all layers are essential to overcome these challenges. In particular, the physical layer (PHY) transmission is required to achieve certain link reliability, data rate, and latency. In modern digital communications systems, the transmission is performed by means of a digital signal processing module that derives analog hardware. The performance of the analog part is influenced by the quality of the hardware and the baseband signal denoted as waveform. In most of the modern systems such as fifth generation (5G) and WiFi, orthogonal frequency division multiplexing (OFDM) is adopted as a favorite waveform due to its low-complexity advantages in terms of signal processing. However, OFDM requires strict requirements on hardware quality. Many devices are equipped with simplified analog hardware to reduce the cost. In this case, OFDM does not work properly as a result of its high peak-to-average power ratio (PAPR) and sensitivity to synchronization errors. To tackle these problems, many waveforms design have been recently proposed in the literature. Some of these designs are modified versions of OFDM or based on conventional single subcarrier. Moreover, multicarrier frameworks, such as generalized frequency division multiplexing (GFDM), have been proposed to realize varieties of conventional waveforms. Furthermore, recent studies show the potential of using non-conventional waveforms for increasing the link reliability with affordable complexity. Based on that, flexible waveforms and transmission techniques are necessary to adapt the system for different hardware and channel constraints in order to fulfill the applications requirements while optimizing the resources. The objective of this thesis is to provide a holistic view of waveforms and the related multiple access (MA) techniques to enable efficient study and evaluation of different approaches. First, the wireless communications system is reviewed with specific focus on the impact of hardware impairments and the wireless channel on the waveform design. Then, generalized model of waveforms and MA are presented highlighting various special cases. Finally, this work introduces low-complexity architectures for hardware implementation of flexible waveforms. Integrating such designs with software-defined radio (SDR) contributes to the development of practical real-time flexible PHY.:1 Introduction 1.1 Baseband transmission model 1.2 History of multicarrier systems 1.3 The state-of-the-art waveforms 1.4 Prior works related to GFDM 1.5 Objective and contributions 2 Fundamentals of Wireless Communications 2.1 Wireless communications system 2.2 RF transceiver 2.2.1 Digital-analogue conversion 2.2.2 QAM modulation 2.2.3 Effective channel 2.2.4 Hardware impairments 2.3 Waveform aspects 2.3.1 Single-carrier waveform 2.3.2 Multicarrier waveform 2.3.3 MIMO-Waveforms 2.3.4 Waveform performance metrics 2.4 Wireless Channel 2.4.1 Line-of-sight propagation 2.4.2 Multi path and fading process 2.4.3 General baseband statistical channel model 2.4.4 MIMO channel 2.5 Summary 3 Generic Block-based Waveforms 3.1 Block-based waveform formulation 3.1.1 Variable-rate multicarrier 3.1.2 General block-based multicarrier model 3.2 Waveform processing techniques 3.2.1 Linear and circular filtering 3.2.2 Windowing 3.3 Structured representation 3.3.1 Modulator 3.3.2 Demodulator 3.3.3 MIMO Waveform processing 3.4 Detection 3.4.1 Maximum-likelihood detection 3.4.2 Linear detection 3.4.3 Iterative Detection 3.4.4 Numerical example and insights 3.5 Summary 4 Generic Multiple Access Schemes 57 4.1 Basic multiple access and multiplexing schemes 4.1.1 Infrastructure network system model 4.1.2 Duplex schemes 4.1.3 Common multiplexing and multiple access schemes 4.2 General multicarrier-based multiple access 4.2.1 Design with fixed set of pulses 4.2.2 Computational model 4.2.3 Asynchronous multiple access 4.3 Summary 5 Time-Frequency Analyses of Multicarrier 5.1 General time-frequency representation 5.1.1 Block representation 5.1.2 Relation to Zak transform 5.2 Time-frequency spreading 5.3 Time-frequency block in LTV channel 5.3.1 Subcarrier and subsymbol numerology 5.3.2 Processing based on the time-domain signal 5.3.3 Processing based on the frequency-domain signal 5.3.4 Unified signal model 5.4 summary 6 Generalized waveforms based on time-frequency shifts 6.1 General time-frequency shift 6.1.1 Time-frequency shift design 6.1.2 Relation between the shifted pulses 6.2 Time-frequency shift in Gabor frame 6.2.1 Conventional GFDM 6.3 GFDM modulation 6.3.1 Filter bank representation 6.3.2 Block representation 6.3.3 GFDM matrix structure 6.3.4 GFDM demodulator 6.3.5 Alternative interpretation of GFDM 6.3.6 Orthogonal modulation and GFDM spreading 6.4 Summary 7 Modulation Framework: Architectures and Applications 7.1 Modem architectures 7.1.1 General modulation matrix structure 7.1.2 Run-time flexibility 7.1.3 Generic GFDM-based architecture 7.1.4 Flexible parallel multiplications architecture 7.1.5 MIMO waveform architecture 7.2 Extended GFDM framework 7.2.1 Architectures complexity and flexibility analysis 7.2.2 Number of multiplications 7.2.3 Hardware analysis 7.3 Applications of the extended GFDM framework 7.3.1 Generalized FDMA 7.3.2 Enchantment of OFDM system 7.4 Summary 7 Conclusions and Future work