Fundamental study of underfill void formation in flip chip assembly

Flip Chip in Package (FCIP) has been developed to achieve the assembly process with area array interconnects. Particularly, a high I/O count coupled with finer pitch area array interconnects structured FCIP can be achieved using no-flow underfill assembly process. Using the assembly process, a high, stable yield assembly process recently reported with eutectic lead-tin solder interconnections, 150 µm pitch, and I/O counts in excess of 3000. The assembly process reported created a large number of voids among solder interconnects in FCIP. The voids formed among solder interconnections can propagate, grow, and produce defects such as solder joint cracking and solder bridging. Moreover, these voids can severely reduce reliability performance. Indeed, many studies were conducted to examine the void formation in FCIP. Based on the studies, flip chip geometric design, process conditions, and material formulation have been considered as the potential causes of void formation. However, the present research won't be able to identify the mechanism of void formation, causing a lot of voids in assembly process without consideration of chemical reaction in the assembly process with a fine-pitch, high I/O density FCIP. Therefore, this research will present process technology necessary to achieve high yields in FCIP assemblies using no-flow underfills and investigate the underlying problem of underfill void formation in these assemblies. The plausible causes of void formation will be investigated using experimental techniques. The techniques will identify the primary source of the void formation. Besides, theoretical models will be established to predict the number of voids and to explain the growth behavior of voids in the FCIP. The established theoretical models will be verified by experiments. These models will validate with respect to the relationship between process parameters to achieve a high yield and to minimize voids in FCIP assemblies using no-flow underfill materials regarding process as well as material stand points. Eventually, this research provides design guideline achieving a high, stable yield and void-free assembly process.Ph.D.Committee Chair: Baldwin, Daniel; Committee Member: Colton, Jonathan; Committee Member: Ghiaasiaan, Mostafa; Committee Member: Moon, Jack; Committee Member: Tummala, Ra

Ultra thin ultrafine-pitch chip-package interconnections for embedded chip last approach

Ever growing demands for portability and functionality have always governed the electronic technology innovations. IC downscaling with Moore s law and system miniaturization with System-On-Package (SOP) paradigm has resulted and will continue to result in ultraminiaturized systems with unprecedented functionality at reduced cost. The trend towards 3D silicon system integration is expected to downscale IC I/O pad pitches from 40µm to 1- 5 µm in future. Device- to- system board interconnections are typically accomplished today with either wire bonding or solders. Both of these are incremental and run into either electrical or mechanical barriers as they are extended to higher density of interconnections. Alternate interconnection approaches such as compliant interconnects typically require lengthy connections and are therefore limited in terms of electrical properties, although expected to meet the mechanical requirements. As supply currents will increase upto 220 A by 2012, the current density will exceed the maximum allowable current density of solders. The intrinsic delay and electromigration in solders are other daunting issues that become critical at nanometer size technology nodes. In addition, formation of intermetallics is also a bottleneck that poses significant mechanical issues. Recently, many research groups have investigated various techniques for copper-copper direct bonding. Typically, bonding is carried out at 400oC for 30 min followed by annealing for 30 min. High thermal budget in such process makes it less attractive for integrated systems because of the associated process incompatibilities. In the present study, copper-copper bonding at ultra fine-pitch using advanced nano-conductive and non-conductive adhesives is evaluated. The proposed copper-copper based interconnects using advanced conductive and non-conductive adhesives will be a new fundamental and comprehensive paradigm to solve all the four barriers: 1) I/O pitch 2) Electrical performance 3) Reliability and 4) Cost. This thesis investigates the mechanical integrity and reliability of copper-copper bonding using advanced adhesives through test vehicle fabrication and reliability testing. Test vehicles were fabricated using low cost electro-deposition techniques and assembled onto glass carrier. Experimental results show that proposed copper-copper bonding using advanced adhesives could potentially meet all the system performance requirements for the emerging micro/nano-systems.M.S.Committee Chair: Prof. Rao R Tummala; Committee Member: Dr. Jack Moon; Committee Member: Dr. P M Ra

Electrodeposition and characterisation of lead-free solder alloys for electronics interconnection

Conventional tin-lead solder alloys have been widely used in electronics interconnection owing to their properties such as low melting temperature, good ductility and excellent wettability on copper and other substrates. However, due to the worldwide legislation addressing the concern over the toxicity of lead, the usage of lead-containing solders has been phased out, thus stimulating substantial efforts on lead-free alternatives, amongst which eutectic Sn-Ag and Sn-Cu, and particularly Sn-Ag-Cu alloys, are promising candidates as recommended by international parties. To meet the increasing demands of advanced electronic products, high levels of integration of electronic devices are being developed and employed, which is leading to a reduction in package size, but with more and more input/output connections. Flip chip technology is therefore seen as a promising technique for chip interconnection compared with wire bonding, enabling higher density, better heat dissipation and a smaller footprint. This thesis is intended to investigate lead-free (eutectic Sn-Ag, Sn-Cu and Sn-Ag-Cu) wafer level solder bumping through electrodeposition for flip chip interconnection, as well as electroplating lead-free solderable finishes on electronic components. The existing knowledge gap in the electrochemical processes as well as the fundamental understanding of the resultant tin-based lead-free alloys electrodeposits are also addressed. For the electrodeposition of the Sn-Cu solder alloys, a methanesulphonate based electrolyte was established, from which near-eutectic Sn-Cu alloys were achieved over a relatively wide process window of current density. The effects of methanesulphonic acid, thiourea and OPPE (iso-octyl phenoxy polyethoxy ethanol) as additives were investigated respectively by cathodic potentiodynamic polarisation curves, which illustrated the resultant electrochemical changes to the electrolyte. Phase identification by X-ray diffraction showed the electrodeposits had a biphasic structure (β-Sn and Cu6Sn5). Microstructures of the Sn-Cu electrodeposits were comprehensively characterised, which revealed a compact and crystalline surface morphology under the effects of additives, with cross-sectional observations showing a uniform distribution of Cu6Sn5 particles predominantly along β-Sn grain boundaries. The electrodeposition of Sn-Ag solder alloys was explored in another pyrophosphate based system, which was further extended to the application for Sn-Ag-Cu solder alloys. Cathodic potentiodynamic polarisation demonstrated the deposition of noble metals, Ag or Ag-Cu, commenced before the deposition potential of tin was reached. The co-deposition of Sn-Ag or Sn-Ag-Cu alloy was achieved with the noble metals electrodepositing at their limiting current densities. The synergetic effects of polyethylene glycol (PEG) 600 and formaldehyde, dependent on reaching the cathodic potential required, helped to achieve a bright surface, which consisted of fine tin grains (~200 nm) and uniformly distributed Ag3Sn particles for Sn-Ag alloys and Ag3Sn and Cu6Sn5 for Sn-Ag-Cu alloys, as characterised by microstructural observations. Near-eutectic Sn-Ag and Sn-Ag-Cu alloys were realised as confirmed by compositional analysis and thermal measurements. Near-eutectic lead-free solder bumps of 25 μm in diameter and 50 μm in pitch, consisting of Sn-Ag, Sn-Cu or Sn-Ag-Cu solder alloys depending on the process and electrolyte employed, were demonstrated on wafers through the electrolytic systems developed. Lead-free solder bumps were further characterised by material analytical techniques to justify the feasibility of the processes developed for lead-free wafer level solder bumping

Copper to copper bonding by nano interfaces for fine pitch interconnections and thermal applications

Ever growing demands for portability and functionality have always governed the electronic technology innovations. IC downscaling with Moore s law at IC level and system miniaturization with System-On-Package (SOP) paradigm at system level, have resulted and will continue to result in ultraminiaturized systems with unprecedented functionality at reduced cost. However, system miniaturization poses several electrical and thermal challenges that demand innovative solutions including advanced materials, bonding and assembly techniques. Heterogeneous material and device integration for thermal structures and IC assembly are limited by the bonding technology and the electrical and thermal impedance of the bonding interfaces. Solder - based bonding technology that is prevalent today is a major limitation to future systems. The trend towards miniaturized systems is expected to drive downscaling of IC I/O pad pitches from 40µm to 1- 5µm in future. Solder technology imposes several pitch, processability and cost restrictions at such fine pitches. Furthermore, according to International Technology Roadmap for Semiconductors (ITRS-2006), the supply current in high performance microprocessors is expected to increase to 220 A by 2012. At such supply current, the current density will exceed the maximum allowable current density of solders. The intrinsic delay and electromigration in solders are other daunting issues that become critical at nanometer sized technology nodes. In addition, formation of intermetallics is also a bottleneck that poses significant mechanical issues. Similarly, thermal power dissipation is growing to unprecedented high with a projected power of 198 W by 2008 (ITRS 2006). Present thermal interfaces are not adequate for such high heat dissipation. Recently, copper based thin film bonding has become a promising approach to address the abovementioned challenges. However, copper-copper direct bonding without using solders has not been studied thoroughly. Typically, bonding is carried out at 400oC for 30 min followed by annealing for 30 min. High thermal budget in such process makes it less attractive for integrated systems because of the associated process incompatibilities. Hence, there is a need to develop a novel low temperature copper to copper bonding process. In the present study, nanomaterials - based copper-to-copper bonding is explored and developed as an alternative to solder-based bonding. To demonstrate fine pitch bonding, the patterning of these nanoparticles is crucial. Therefore, two novel self-patterning techniques based on: 1.) Selective wetting and 2.) Selective nanoparticle deposition, are developed to address this challenge. Nanoparticle active layer facilitates diffusion and, thus, a reliable bond can be achieved using less thermal budget. Quantitative characterization of the bonding revealed good metallurgical bonding with very high bond strength. This has been confirmed by several morphological and structural characterizations. A 30-micron pitch IC assembly test vehicle is used to demonstrate fine pitch patternability and bonding. In conclusion, novel nanoparticle synthesis and patterning techniques were developed and demonstrated for low-impedance and low-cost electrical and thermal interfaces.M.S.Committee Chair: Rao R. Tummala; Committee Member: C. P. Wong; Committee Member: P. M. Ra

Thermo-Mechanical Reliability and Electrical Performance of Indium Interconnects and Under Bump Metallization

This thesis presents reliability analysis of indium interconnects and Under Bump Metallization (UBM) in flip chip devices. Flip chip assemblies with the use of bump interconnections are frequently used, especially in high density, three-dimensional electronic devices. Currently there are many methods for interconnect bumping, all of which require UBM. The UBM is required for interconnection, diffusion resistance and quality electrical contact between substrate and device. Bonded silicon test vehicles were comprised of Indium bumps and three UBM compositions: Ti/Ni/Au (200\xc5/1000\xc5/500\xc5), Ti/Ni (200\xc5/1000\xc5), Ni (1000\xc5). UBM and indium were deposited by evaporation and exposed to unbiased accelerated temperature cycling(-55°C to 125°C, 15°C/min ramp rate). Finite Element Analysis (FEA) simulations were used to gain understanding of non-linear strain behavior of indium interconnects during temperature cycling. Experimental testing coupled with FEA simulations facilitated cycle-to-failure calculations. FEA results show plastic strain concentrations within indium bump below failure limits. It has been demonstrated that fabrication of Ti/Ni/Au, Ti/Ni, and Ni UBM stacks performed reliably within infant mortality failure region

Study of intermetallic compound layer formation, growth and evaluation of shear strength of lead-free solder joints

Solder joints play a very important role in electronic products as the integrity of electronics packaging and assembly rests on the quality of these connections. The increasing demands for higher performance, lower cost, and miniaturisation in hand-held and consumer electronic products have led to the use of dense interconnections. This miniaturization trend means that solder joint reliability remains an important challenge with surface mount electronics assembly, especially those used in hostile environments, and applications such as automobile, aerospace and other safety critical operations. One of the most important factors which are known to affect solder joint reliability is the thickness of intermetallic compound (IMC) layer formed between the solder and the substrate. Although the formation of an IMC layer signifies good bonding between the solder and substrate, its main disadvantage is that it is also known to be the most brittle part of the solder joint. Thus as the miniaturisation trend continues, and solder joints become even smaller in size, the nature and impact of IMC layer thickness on solder joint reliability becomes even more of a concern with the introduction of new lead-free soldering. Other factors which are known to affect solder joint reliability include the bonding strength, the voiding percentage in joints, the size of the voids and their location within the joint. The work reported in this thesis on formation and growth of intermetallic compound layer, and evaluation of the shear strength of lead-free solder joints is divided into four main parts. The first part of the study is concerned with understanding of the effect of pad sizes on Inter-metallic compound layer formation and growth for lead-free solder joints. The second part concerns the study of the effect of temperature cycling and reflow profiles on intermetallic growth between Sn-Ag-Cu alloy and Cu substrate. The third part of the study concerns the investigation of the effect of reflow soldering profile optimization on solder volumes using design of experiment technique. The focus of the final part of the study is the investigation of the effect of Inter-metallic Compound thickness on shear strength of 1206 surface mount chip resistor. The results from the experimental work showed that the pad size has very little influence on the growth of the IMC. The result also shows that the growth of IMC depends on diffusion rate, temperature and time according to the power-law model; and that the IMC layer thickness is independent of pad size. The significance of this result is that with further reductions in joint size (with IMC layer thickness remaining the same), the ratio of the IMC layer thickness to solder joint size will increase and adversely impact the joint reliability. The work carried out on ageing temperatures and reflow profiles of Sn-Ag-Cu alloy and Cu substrate also showed the reaction-diffusion mechanism of intermetallic compound formation and growth in solder joints. The study also showed that the most significant factor in achieving lower IMC layer thickness and fine microstructures is the time to peak temperature of the reflow soldering process. The effect of IMC layer thickness on the shear strength of Sn-Ag-Cu solder joints was investigated. The relationship of shear strength, interfacial microstructures and fracture surfaces was considered. It is clear that formation of continuous Cu-Sn and SnNiCu layers are the reason for the weak interface strength. The results show that the shear strength of solder joints decreases with increasing ageing time. The results of this study have been disseminated through journal and conference publications and will be of interest to R&D personnel working in the area of high temperature electronics and in particular those working in the field of automotive electronics

Novel fine pitch interconnection methods using metallised polymer spheres

There is an ongoing demand for electronics devices with more functionality while reducing size and cost, for example smart phones and tablet personal computers. This requirement has led to significantly higher integrated circuit input/output densities and therefore the need for off-chip interconnection pitch reduction. Flip-chip processes utilising anisotropic conductive adhesives anisotropic conductive films (ACAs/ACFs) have been successfully applied in liquid crystal display (LCD) interconnection for more than two decades. However the conflict between the need for a high particle density, to ensure sufficient the conductivity, without increasing the probability of short circuits has remained an issue since the initial utilization of ACAs/ACFs for interconnection. But this issue has become even more severe with the challenge of ultra-fine pitch interconnection. This thesis advances a potential solution to this challenge where the conductive particles typically used in ACAs are selectively deposited onto the connections ensuring conductivity without bridging. The research presented in this thesis work has been undertaken to advance the fundamental understanding of the mechanical characteristics of micro-sized metal coated polymer particles (MCPs) and their application in fine or ultra-fine pitch interconnections. This included use of a new technique based on an in-situ nanomechanical system within SEM which was utilised to study MCP fracture and failure when undergoing deformation. Different loading conditions were applied to both uncoated polymer particles and MCPs, and the in-situ system enables their observation throughout compression. The results showed that both the polymer particles and MCP display viscoelastic characteristics with clear strain-rate hardening behaviour, and that the rate of compression therefore influences the initiation of cracks and their propagation direction. Selective particle deposition using electrophoretic deposition (EPD) and magnetic deposition (MD) of Ni/Au-MCPs have been evaluated and a fine or ultra-fine pitch deposition has been demonstrated, followed by a subsequent assembly process. The MCPs were successfully positively charged using metal cations and this charging mechanism was analysed. A new theory has been proposed to explain the assembly mechanism of EPD of Ni/Au coated particles using this metal cation based charging method. The magnetic deposition experiments showed that sufficient magnetostatic interaction force between the magnetized particles and pads enables a highly selective dense deposition of particles. Successful bonding to form conductive interconnections with pre-deposited particles have been demonstrated using a thermocompression flip-chip bonder, which illustrates the applicable capability of EPD of MCPs for fine or ultra-fine pitch interconnection

Interfacial Reactions And Electromigration In Lead-Free Solder Joints With Copper And Au-Ni Surface Finished Copper Substrates

Pencirian aloi pateri tanpa plumbum (Sn-9Zn, Sn-8Zn-3Bi dan Sn-3Ag-0.5Cu) ke atas substrat kumprum tanpa salutan dan yang disalut dengan Au-Ni telah dilakukan. Keputusan menunjukkan kebolehbasahan bagi ketiga-tiga aloi pateri ke atas substrat kuprum adalah baik pada suhu yang telah ditetapkan. Ukuran sudut sentuh dan daya basahan menunjukkan pembasahan yang baik telah tercapai. Properties of lead free solder alloys (Sn-9Zn, Sn-8Zn-3Bi and Sn-3Ag-0.5Cu) on Au-Ni surface finished copper and copper substrates were investigated. Results obtained showed good wetting of all three solder alloys on Au-Ni surface finished substrate at appropriate temperatures. Contact angle measurement and wetting force results reaffirmed that good wetting of solder alloys on substrate was achieved