Aspects of practical implementations of PRAM algorithms

The PRAM is a shared memory model of parallel computation which abstracts away from inessential engineering details. It provides a very simple architecture independent model and provides a good programming environment. Theoreticians of the computer science community have proved that it is possible to emulate the theoretical PRAM model using current technology. Solutions have been found for effectively interconnecting processing elements, for routing data on these networks and for distributing the data among memory modules without hotspots. This thesis reviews this emulation and the possibilities it provides for large scale general purpose parallel computation. The emulation employs a bridging model which acts as an interface between the actual hardware and the PRAM model. We review the evidence that such a scheme crn achieve scalable parallel performance and portable parallel software and that PRAM algorithms can be optimally implemented on such practical models. In the course of this review we presented the following new results: 1. Concerning parallel approximation algorithms, we describe an NC algorithm for finding an approximation to a minimum weight perfect matching in a complete weighted graph. The algorithm is conceptually very simple and it is also the first NC-approximation algorithm for the task with a sub-linear performance ratio. 2. Concerning graph embedding, we describe dense edge-disjoint embeddings of the complete binary tree with n leaves in the following n-node communication networks: the hypercube, the de Bruijn and shuffle-exchange networks and the 2-dimcnsional mesh. In the embeddings the maximum distance from a leaf to the root of the tree is asymptotically optimally short. The embeddings facilitate efficient implementation of many PRAM algorithms on networks employing these graphs as interconnection networks. 3. Concerning bulk synchronous algorithmics, we describe scalable transportable algorithms for the following three commonly required types of computation; balanced tree computations. Fast Fourier Transforms and matrix multiplications

Control and reliability of optical networks in multiprocessors

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1993.Includes bibliographical references (leaves 138-142).by James Jonathan Olsen.Ph.D

Improved Routing and Sorting on Multibutterflies

This paper shows that an N-node AKS network (as described by Paterson) can be embedded in a 3N/2-node degree8 multibutterfly network with load 1, congestion 1, and dilation 2. The result has several implications, including the first deterministic algorithms for sorting and finding the median of n log n keys on an n-input multibutterfly in O(log n) time, a work-efficient deterministic algorithm for finding the median of n log² n log log n keys on an n-input multibutterfly in O(log n log log n) time, and a three-dimensional VLSI layout for the n-input AKS network with volume O(n 3=2 ). While these algorithms are not practical, they provide further evidence of the robustness of multibutterfly networks. We also present a separate, and more practical, deterministic algorithm for routing h relations on an n-input multibutterfly in O(h + log n) time. Previously, only algorithms for solving h one-to-one routing problems were known. Finally, we show that a 2-folded butterfly, whose i..

Improved Routing and Sorting on Multibutterflies

This paper shows that an N-node AKS network (as described by Paterson) can be embedded in a (3N/2)-node twinbutterfly network (i.e., a multibutterfly constructed by superimposing two butterfly networks) with load 1, congestion 1, and dilation 2. The result has several implications, including the first deterministic algorithms for sorting and finding the median of n log n items on an n-input multibutterfly in O(log n) time, a work-efficient deterministic algorithm for finding the median of n log2 n log log n items on an n-input multibutterfly in O(log n log log n) time, and a three-dimensional VLSI layout for the n-input AKS network with volume O(n3/2). While these algorithms are not practical, they provide further evidence of the robustness of multibutterfly networks. We also present a separate, and more practical, deterministic algorithm for routing h-relations on an n-input multibutterfly in O(h + log n) time. Previously, only algorithms for solving h one-to-one routing problems were known. Finally, we show that a twinbutterfly, whose individual splitters do not exhibit expansion, can emulate a bounded-degree multibutterfly with (α, β)-expansion, for any α · β<

Deterministic Routing of h-relations on the Multibutterfly

In this paper we devise an optimal deterministic algorithm for routing h-relations on-line on an N -input/output multibutterfly. The algorithm, which is obtained by generalizing the circuit-switching techniques of [3], routes any h-relation with messages of X bits in O , h#X + log N # # steps in the bit model, and in O , hdX= log Ne + log N # communication steps in the word model. Unlike other recently developed algorithms, our algorithm does not need extra levels of expanders, hence minimizes the layout area. Moreover, the network topology does not depend on h. 1. Introduction A communication network can be regarded as a graph whose nodes represent input/output ports or internal switches, and whose edges represent direct links between pairs of nodes. A routing problem for such a network is defined as a set of point-to-point messages to be delivered from the inputs to the outputs. A solution to a routing problem requires selecting a path in the network for each message, and sch..