Design of Energy Harvester Module with a Low RF Power Input for UHF RFID Tag

An UHF RFID system is required to be able to operate at long range coverage, typically at 1-4 m. As a result, the RF signal power received at RFID Tag is very low, typically at -10 dBm. Moreover, practically most of commercially used RFID Tag is passive, which means that it solely relies on the RF signal transmitted from the RFID reader as the power source. Therefore, it is mandatory and critical to design an efficient and low input power RFID Tag system. In this paper, an energy harvester module for UHF RFID Tag, which is able to work at low RF input signal power and generate a stable DC voltage output, is designed. The module is able to operate at a very low RF input power as low as -10 dBm or equal to 100 mVpeak of induced voltage. To obtain such performance, a modified and optimized rectifier-using a Dynamic Vth Cancellation technique, is designed. By using this technique, the rectifier is able to produce an efficient and a high output voltage. Additionally, bandgap reference and voltage regulator circuits are designed to be independent of power supply and temperature variation. As the result, a stable DC power supply output is able to be generated. All the circuits are designed on Silterra 130nm CMOS technology. This technology allows us to design the transistor to operate at a low threshold voltage of 0.1 V, which is very suitable for the application of low input power UHF RFID Tag system

Study on Analog Front End of Passive UHF RFID Transponder

In this paper, an overview of passive Ultra High Frequency (UHF) Radio Frequency Identification (RFID) is presented. This literature review emphasis on the analog front end part of the RFID transponder based on several published papers conducted by previous researchers. A passive UHF RFID transponder chip design was proposed using 0.18 μm standard CMOS process. It is estimated to have power of 1μW and high efficiency that greater than 32%. This design will work in the range of frequency between 900MHz to 960MHz

Architecture of Micro Energy Harvesting Using Hybrid Input of RF, Thermal and Vibration for Semi-Active RFID Tag

This research work presents a novel architecture of Hybrid Input Energy Harvester (HIEH) system for semi-active Radio Frequency Identification (RFID) tags. The proposed architecture consists of three input sources of energy which are radio frequency signal, thermal and vibration. The main purpose is to solve the semi-active RFID tags limited lifespan issues due to the need for batteries to power their circuitries. The focus will be on the rectifiers and DC-DC converter circuits with an ultra-low power design to ensure low power consumption in the system. The design architecture will be modelled and simulated using PSpice software, Verilog coding using Mentor Graphics and real-time verification using field-programmable gate array board before being implemented in a 0.13 µm CMOS technology. Our expectations of the results from this architecture are it can deliver 3.3 V of output voltage, 6.5 mW of output power and 90% of efficiency when all input sources are simultaneously harvested. The contribution of this work is it able to extend the lifetime of semi-active tag by supplying electrical energy continuously to the device. Thus, this will indirectly  reduce the energy limitation problem, eliminate the dependency on batteries and make it possible to achieve a batteryless device.This research work presents a novel architecture of Hybrid Input Energy Harvester (HIEH) system for semi-active Radio Frequency Identification (RFID) tags. The proposed architecture consists of three input sources of energy which are radio frequency signal, thermal and vibration. The main purpose is to solve the semi-active RFID tags limited lifespan issues due to the need for batteries to power their circuitries. The focus will be on the rectifiers and DC-DC converter circuits with an ultra-low power design to ensure low power consumption in the system. The design architecture will be modelled and simulated using PSpice software, Verilog coding using Mentor Graphics and real-time verification using field-programmable gate array board before being implemented in a 0.13 µm CMOS technology. Our expectations of the results from this architecture are it can deliver 3.3 V of output voltage, 6.5 mW of output power and 90% of efficiency when all input sources are simultaneously harvested. The contribution of this work is it able to extend the lifetime of semi-active tag by supplying electrical energy continuously to the device. Thus, this will indirectly  reduce the energy limitation problem, eliminate the dependency on batteries and make it possible to achieve a batteryless device

Optimized Hardware Implementations of Lightweight Cryptography

Radio frequency identification (RFID) is a key technology for the Internet of Things era. One important advantage of RFID over barcodes is that line-of-sight is not required between readers and tags. Therefore, it is widely used to perform automatic and unique identification of objects in various applications, such as product tracking, supply chain management, and animal identification. Due to the vulnerabilities of wireless communication between RFID readers and tags, security and privacy issues are significant challenges. The most popular passive RFID protocol is the Electronic Product Code (EPC) standard. EPC tags have many constraints on power consumption, memory, and computing capability. The field of lightweight cryptography was created to provide secure, compact, and flexible algorithms and protocols suitable for applications where the traditional cryptographic primitives, such as AES, are impractical. In these lightweight algorithms, tradeoffs are made between security, area/power consumption, and throughput. In this thesis, we focus on the hardware implementations and optimizations of lightweight cryptography and present the Simeck block cipher family, the WG-8 stream cipher, the Warbler pseudorandom number generator (PRNG), and the WGLCE cryptographic engine. Simeck is a new family of lightweight block ciphers. Simeck takes advantage of the good components and design ideas of the Simon and Speck block ciphers and it has three instances with different block and key sizes. We provide an extensive exploration of different hardware architectures in ASICs and show that Simeck is smaller than Simon in terms of area and power consumption. For the WG-8 stream cipher, we explore four different approaches for the WG transformation module, where one takes advantage of constant arrays and the other three benefit from the tower field constructions of the finite field \F_{2^8} and also efficient basis conversion matrices. The results in FPGA and ASICs show that the constant arrays based method is the best option. We also propose a hybrid design to improve the throughput with a little additional hardware. For the Warbler PRNG, we present the first detailed and smallest hardware implementations and optimizations. The results in ASICs show that the area of Warbler with throughput of 1 bit per 5 clock cycles (1/5 bpc) is smaller than that of other PRNGs and is in fact smaller than that of most of the lightweight primitives. We also optimize and improve the throughput from 1/5 bpc to 1 bpc with a little additional area and power consumption. Finally, we propose a cryptographic engine WGLCE for passive RFID systems. We merge the Warbler PRNG and WG-5 stream cipher together by reusing the finite state machine for both of them. Therefore, WGLCE can provide data confidentiality and generate pseudorandom numbers. After investigating the design rationales and hardware architectures, our results in ASICs show that WGLCE meets the constraints of passive RFID systems

A low power signal front-end for passive UHF RFID transponders with a new clock recovery circuit.

Chan, Chi Fat.Thesis (M.Phil.)--Chinese University of Hong Kong, 2009.Includes bibliographical references.Abstracts in English and Chinese.Abstract --- p.2摘要 --- p.5Acknowledgement --- p.7Table of Contents --- p.9List of Figures --- p.11List of Tables --- p.14Chapter 1. --- Introduction --- p.15Chapter 1.2. --- Research Objectives --- p.16Chapter 1.3. --- Thesis Organization --- p.18Chapter 1.4. --- References --- p.19Chapter 2. --- Overview of Passive UHF RFID Transponders --- p.20Chapter 2.1. --- Types of RFID Transponders and Design Challenges of Passive RFID Transponder --- p.20Chapter 2.2. --- Selection of Carrier Frequency --- p.22Chapter 2.3. --- Description of Transponder Construction --- p.22Chapter 2.3.1. --- Power-Generating Circuits --- p.23Chapter 2.3.2. --- Base Band Processor --- p.28Chapter 2.3.3. --- Signal Front-End --- p.29Chapter 2.4. --- Summary --- p.30Chapter 2.5. --- References --- p.31Chapter 3. --- ASK Demodulator for EPC C-l G-2 Transponder --- p.32Chapter 3.1. --- ASK Demodulator Design Considerations --- p.32Chapter 3.1.1. --- Recovered Envelope Distortion --- p.32Chapter 3.1.2. --- Input Power Level Considerations --- p.34Chapter 3.1.3. --- Input RF power Intercepted by ASK Demodulator --- p.36Chapter 3.2. --- ASK Demodulator Design From [3-4] --- p.36Chapter 3.2.1. --- Envelope Waveform Recovery Design --- p.37Chapter 3.2.1.1. --- Voltage Multiplier Branch for Generating Venv --- p.39Chapter 3.2.1.2. --- Voltage Multiplier Branch for Generating Vref --- p.41Chapter 3.2.2. --- Design Considerations for Sensitivity of ASK Demodulator --- p.41Chapter 3.2.3. --- RF Input Power Sharing with Voltage Multiplier --- p.44Chapter 3.2.4. --- ASK Demodulator and Voltage Multiplier Integrated Estimations for Maximum RF Power Input --- p.47Chapter 3.2.5. --- Measurement result and Discussion --- p.49Chapter 3.3. --- Proposed Envelope Detector Circuit --- p.52Chapter 3.3.1. --- Sensitivity Estimation --- p.52Chapter 3.3.2. --- Maximum Tolerable Input Power Estimation --- p.53Chapter 3.3.3. --- Envelope Waveform Recovery of the Proposed Envelope Detector --- p.54Chapter 3.4. --- Summary --- p.57Chapter 3.5. --- References --- p.58Chapter 4. --- Clock Generator for EPC C-l G-2 Transponder --- p.59Chapter 4.1. --- Design Challenges Overview of Clock Generator --- p.59Chapter 4.2. --- Brief Review of PIE Symbols in EPC C1G2 Standard --- p.62Chapter 4.3. --- Proposed Clock Recovery Circuit Based on PIE Symbols for Clock Frequency Calibration --- p.64Chapter 4.3.1. --- Illustration on PIE Symbols for Clock Frequency Calibration --- p.64Chapter 4.3.2. --- Symbol time-length counter --- p.72Chapter 4.3.3. --- The M2.56MHZ Reference Generator and Sampling Frequency Requirement --- p.75Chapter 4.3.4. --- Symbol Length Reconfiguration for Different Tari and FLL Stability --- p.80Chapter 4.3.5. --- Frequency Detector and Loop Filter --- p.83Chapter 4.3.6. --- Proposed DCO Design --- p.84Chapter 4.3.7. --- Measurement Results and Discussions --- p.88Chapter 4.3.7.1. --- Frequency Calibration Measurement Results --- p.89Chapter 4.3.7.2. --- Number x and Tari Variation --- p.92Chapter 4.3.7.3. --- Temperature and Supply Variation --- p.93Chapter 4.3.7.4. --- Transient Supply Variation --- p.94Chapter 4.3.8. --- Works Comparison --- p.95Chapter 4.4. --- Clock Generator with Embedded PIE Decoder --- p.96Chapter 4.4.1. --- Clock Generator for Transponder Review --- p.96Chapter 4.4.2. --- PIE Decoder Review --- p.97Chapter 4.4.3. --- Proposed Clock Generator with Embedded PIE Decoder --- p.97Chapter 4.4.4. --- Measurement Results and Discussions --- p.100Chapter 4.5. --- Summary --- p.103Chapter 4.6. --- References --- p.105Chapter 5. --- ASK Modulator --- p.107Chapter 5.1. --- Introduction to ASK Modulator in RFD Transponder --- p.107Chapter 5.2. --- ASK Modulator Design --- p.109Chapter 5.3. --- ASK Modulator Measurement --- p.110Chapter 5.4. --- Summary --- p.113Chapter 5.5. --- References --- p.113Chapter 6. --- Conclusions --- p.114Chapter 6.1. --- Contribution --- p.114Chapter 6.2. --- Future Development --- p.11

Modelagem e projeto de conversores AC/DC de ultrabaixa tensão de operação

Tese (doutorado) - Universidade Federal de Santa Catarina, Centro Tecnológico. Programa de Pós-Graduação em Engenharia ElétricaEsta tese apresenta o desenvolvimento de um modelo analítico e muito simples do circuito retificador, considerando a lei corrente-tensão (exponencial) do diodo, tendo como mérito simplificar um problema relativamente complexo e não linear (retificador) com uma ótima precisão. O modelo mostra-se válido, mesmo para tensões abaixo da tensão térmica, tendo sido testado para um ampla variação de tensão e corrente. São apresentadas equações para a tensão DC de saída, ripple de tensão, transiente durante o startup e eficiência de conversão de potência. Para validação, o modelo é comparado à simulações realizadas em simulador SPICE e a resultados experimentais, mostrando uma ótima precisão. Comparando-se este modelo com outros citados nas referências bibliográficas, este possui a vantagem de ser analítico, mais simples e/ou mais preciso. O desenvolvimento deste modelo torna-se mais importante, à medida que cresce o interesse pela utilização de sensores remotos autoalimentados, e também pelo uso de dispositivos de identificação por rádiofrequência (RFID). O espaço de projeto do conversor AC/DC foi explorado por meio de equações simples e de uma metodologia de projeto desenvolvida para que, através de gráficos, o projetista possa de forma fácil, rápida e com boa precisão, determinar os principais elementos do conversor AC/DC e da rede de adaptação de impedâncias. Para alcançar potências menores na entrada do conversor AC/DC, a metodologia utiliza redes de adaptação de impedâncias para o casamento entre as impedâncias da antena (ou impedância da fonte geradora de sinal AC) e do conversor AC/DC. Além disso, esta metodologia pode ser utilizada para conversores AC/DC com diodos ou transistores conectados como diodos, mesmo que sua equação característica não seja a do diodo exponencial. Para a utilização do conversor AC/DC em circuitos integrados, são estudadas as possibilidades de uso do transistor MOS conectado como diodo operando na região de inversão fraca. Para obter suporte experimental, foram projetados multiplicadores de tensão, com rede de adaptação de impedâncias incorporada ao circuito integrado e também externa ao mesmo, com o objetivo de atingir a menor potência de entrada disponível.This thesis presents a simple analytical model of the rectifier circuit assuming that the diode is characterized by the exponential current-voltage law. The model shown is valid even for voltages below the thermal voltage and it has been tested for a wide range of voltages and currents. Equations are provided for the DC output voltage, ripple voltage, transient during startup and power conversion efficiency. For validation, the model is compared to simulations carried out in SPICE and experimental results, showing a good accuracy. Comparing this model with others cited in the references, this one has the advantage of being analytical, simpler, and more accurate. The development of this model becomes more relevant with the growing use of self powered remote sensors, and radio frequency identification devices (RFID). The design space of the AC/DC converter was explored using a graphic methodology. To operate with reduced power at the input, the methodology uses an impedance adaptation network for the matching between the impedances of the antenna (or the source impedance of the AC signal) and that of the AC/DC converter. Furthermore, this methodology can be used for AC/DC converters with diodes or transistors connected as diodes, even if their characteristic equations are not exponential. To obtain experimental support, voltage multipliers have been designed with impedance adaptation network incorporated into the integrated circuit and also external to it, in order to achieve the lowest possible power at the input

Efficient Hardware Implementations of the Warbler Pseudorandom Number Generator

Pseudorandom number generators (PRNGs) are very important for EPC Class 1 Generation 2 (EPC C1 G2) Radio Frequency Identification (RFID) systems. A PRNG is able to provide a 16-bit random number that is used in many commands of the EPC C1 G2 standard, and it can also be used in future security extensions of the EPC C1 G2 standard, such as mutual authentication protocols between the readers and tags. In this paper, we investigate efficient ASIC hardware implementations of Warbler (a lightweight PRNG), and demonstrate that Warbler can meet the area and power consumption requirements in passive RFID systems. Warbler is built upon three nonlinear feedback shift registers (NLFSRs) and four WG-5 transformation modules. We employ two design options to implement Warbler and three different compilation methods to further optimize the area, maximum operating frequency, and power consumption. We can achieve an area of 498 GEs after the place and route phase in a CMOS 65nm ASIC, with a maximum frequency of 1430 MHz and a total power consumption of 1.239uW at 100 KHz. Accordingly, an area of 534 GEs after the place and route phase, with a maximum frequency of 250 MHz and a total power consumption of 0.296 uW at 100 KHz can be obtained in a CMOS 130nm ASIC. Our results show that the LFSR counter based design is better than the binary counter-based one in terms of area and power consumption. In addition, we show that the areas of WG-5 transformation look-up tables depend on the specific decimation values

Design and implementation of a multi-modal sensor with on-chip security

With the advancement of technology, wearable devices for fitness tracking, patient monitoring, diagnosis, and disease prevention are finding ways to be woven into modern world reality. CMOS sensors are known to be compact, with low power consumption, making them an inseparable part of wireless medical applications and Internet of Things (IoT). Digital/semi-digital output, by the translation of transmitting data into the frequency domain, takes advantages of both the analog and digital world. However, one of the most critical measures of communication, security, is ignored and not considered for fabrication of an integrated chip. With the advancement of Moore\u27s law and the possibility of having a higher number of transistors and more complex circuits, the feasibility of having on-chip security measures is drawing more attention. One of the fundamental means of secure communication is real-time encryption. Encryption/ciphering occurs when we encode a signal or data, and prevents unauthorized parties from reading or understanding this information. Encryption is the process of transmitting sensitive data securely and with privacy. This measure of security is essential since in biomedical devices, the attacker/hacker can endanger users of IoT or wearable sensors (e.g. attacks at implanted biosensors can cause fatal harm to the user). This work develops 1) A low power and compact multi-modal sensor that can measure temperature and impedance with a quasi-digital output and 2) a low power on-chip signal cipher for real-time data transfer

Tri-band CMOS Circuit Dedicated for Ambient RF Energy Harvesting

RÉSUMÉ L'utilisation de systèmes sans fil connait une croissance rapide dans divers domaines tels que les réseaux de téléphonie cellulaire, Wi-Fi, Wi-Max, la radiodiffusion et les communications par satellite. Cette croissance mènera à une quantité considérable d'énergie électromagnétique générée dans l'air ambiant, mais toujours en dessous des limites de sécurité internationales. Ainsi, la recherche au niveau des systèmes de récupération d'énergie RF pour alimenter des appareils électroniques miniaturisés à faible consommation de puissance devient attrayante et prometteuse. Le bloc principal dans un système de récupération d'énergie RF est le redresseur qui détermine l'efficacité et la sensibilité de l'ensemble du système. Étant donné que la puissance RF ambiante est très faible, la quantité d'énergie captée par l'antenne l’est également. En outre, il y a des pertes au niveau du réseau d'adaptation d’impédance qui réduisent encore plus la puissance transmise au bloc redresseur. Par conséquent, la puissance disponible est trop faible pour faire fonctionner des redresseurs classiques. Dans ce mémoire, nous proposons trois redresseurs à trois-étages et à grilles totalement croisées-couplées en utilisant des transistors à faible tension de seuil afin d’opérer à de faibles puissances d'entrée. Les trois redresseurs ont été conçus et intégrés au sein d’une même puce fabriquée en utilisant une technologie CMOS 130nm d’IBM. Ils ont été optimisés à des fréquences de 880MHz, 1960MHz et 2.45GHz respectivement. Les résultats expérimentaux démontrent qu’ils atteignent une efficacité de conversion de puissance maximale de 62%, 62% et 56.2% respectivement. Les mesures montrent également une grande amélioration de l'efficacité à de faibles niveaux de puissance d'entrée. Afin de récupérer l'énergie ambiante de trois principales sources RF au Canada – GSM-850, GSM-1900 et Wi-Fi, un système de redresseur utilisé pour la combinaison de la puissance de ces trois canaux est simulé et analysé. Le système utilise une topologie consistant simplement à connecter les sorties des redresseurs ensemble pour charger le condensateur de charge. En dépit de la grande amélioration de l'efficacité et de la sensibilité dans la plage de 0-5μW, une baisse d'efficacité indésirable se produit aux puissances plus élevées. Ainsi, un nouveau bloc de gestion de l'alimentation est proposé. De plus, une antenne tri-bande est conçue et simulée pour diminuer le volume de l'ensemble du système de récupération d'énergie RF. En particulier, les pertes par réflexion obtenues sont de -25.43dB, -13.92dB et -12.73dB aux fréquences citées plus haut respectivement.---------- ABSTRACT Nowadays, the use of wireless systems has grown rapidly in various domains such as cellular phone networks, Wi-Fi, Wi-Max, radio broadcasting and satellite communications. The growing use of these wireless systems leads to considerable amount of electromagnetic energy generated in ambient air (of course, still below international safety limits). Thus the research in ambient RF energy harvesting system dedicated for powering up low-power-consumption miniaturized electronic devices becomes attractive and promising. The main block in a RF harvesting system is the rectifier which determines the efficiency and sensitivity of the whole system. Since ambient RF power is very low, the amount of power captured by the antenna is extremely low. Besides, there is loss on matching networks, thus the available power given to the rectifier block is too low for traditional rectifiers to operate. Therefore, in this master thesis, three three-stage fully gate cross-coupled rectifiers using low-thresholdvoltage transistors are proposed to overcome the dead zone in low input power range. The three rectifiers optimized at 880MHz, 1960MHz and 2.45GHz frequencies respectively are designed on one chip layout. Their experimental results are retrieved from this custom fabricated integrated circuit using IBM 130nm CMOS technology. They achieve peak efficiencies of 62%, 62% and 56.2% respectively and show great improvements on power conversion efficiency at low input power level. In order to harvest ambient RF energy from the three main RF contributors in Canada – GSM-850, GSM-1900 and Wi-Fi 2.4GHz, a rectifier system used for power combination from these three channels is simulated and analyzed. The system employs a simple topology by connecting the outputs together to charge the load capacitor. In spite of its high improvements on efficiency and sensitivity in 0-5μW range, an undesirable efficiency drop happens at higher input power levels. Thus an idea of power management block is proposed. In addition, a tri-band antenna is designed and simulated so as to decrease the volume of the overall RF energy harvesting system. It achieves return loss of -25.43dB, -13.92dB and - 12.73dB at each desired band respectively