Study on Analog Front End of Passive UHF RFID Transponder

In this paper, an overview of passive Ultra High Frequency (UHF) Radio Frequency Identification (RFID) is presented. This literature review emphasis on the analog front end part of the RFID transponder based on several published papers conducted by previous researchers. A passive UHF RFID transponder chip design was proposed using 0.18 μm standard CMOS process. It is estimated to have power of 1μW and high efficiency that greater than 32%. This design will work in the range of frequency between 900MHz to 960MHz

Optimized hardware implementations of cryptography algorithms for resource-constraint IoT devices and high-speed applications

The advent of technologies, including the Internet and smartphones, has made people’s lives easier. Nowadays, people get used to digital applications for e-business, communicating with others, and sending or receiving sensitive messages. Sending secure data across the private network or the Internet is an open concern for every person. Cryptography plays an important role in privacy, security, and confidentiality against adversaries. Public-key cryptography (PKC) is one of the cryptography techniques that provides security over a large network, such as the Internet of Things (IoT). The classical PKCs, such as Elliptic Curve Cryptography (ECC) and Rivest-Shamir-Adleman (RSA), are based on the hardness of certain number theoretic problems. According to Shor’s algorithm, these algorithms can be solved very efficiently on a quantum computer, and cryptography algorithms will be insecure and weak as quantum computers increase in number. Based on NIST, Lattice-based cryptography (LBC) is one of the accepted quantum-resistant public-key cryptography. Different variants of LBC include Learning With Error (LWE), Ring Learning With Error (Ring-LWE), Binary Ring Learning with Error (Ring-Bin LWE), and etc. AES is also one of the secure cryptography algorithm that has been widely used in different applications and platforms. Also, AES-256 is secure against quantum attack. It is very important to design a crypto-system based on the need and application. In general, each network has three different layers; cloud, edge, and end-node. The cloud and edge layer require to have a high-speed crypto-system, as it is used in high-traffic application to encrypt and decrypt data. Unfortunately, most of the end-node devices are resource-constraint and do not have enough area for security guard. Providing end-to-end security is vital for every network. To mitigate this issue, designing and implementing a lightweight cryto-system for resource-constraint devices is necessary. In this thesis, a high-throughput FPGA implementation of AES algorithm for high-traffic edge applications is introduced. To achieve this goal, some part of the algorithm has been modified to balance the latency. Inner and outer pipelining techniques and loop-unrolling have been employed. The proposed high-speed implementation of AES achieves a throughput of 79.7Gbps, FPGA efficiency of 13.3 Mbps/slice, and frequency of 622.4MHz. Compared to the state-of-the-art work, the proposed design has improved data throughput by 8.02% and FPGA-Eff by 22.63%. Moreover, a lightweight architecture of AES for resource-constraint devices is designed and implemented on FPGA and ASIC. Each module of the architecture is specified in which occupied less area; and some units are shared among different phases. To reduce the power consumption clock gating technique is applied. Application-specific integrated circuit (ASIC) implementation results show a respective improvement in the area over the previous similar works from 35% to 2.4%. Based on the results and NIST report, the proposed design is a suitable crypto-system for tiny devices and can be supplied by low-power devices. Furthermore, two lightweight crypto-systems based on Binary Ring-LWE are presented for IoT end-node devices. For one of them, a novel column-based multiplication is introduced. To execute the column-based multiplication only one register is employed to store the intermediate results. The multiplication unit for the other Binary Ring-LWE design is optimized in which the multiplication is executed in less clock cycles. Moreover, to increase the security for end-node devices, the fault resiliency architecture has been designed and applied to the architecture of Binary Ring-LWE. Based on the implementation results and NIST report, the proposed Binary Ring-LWE designs is a suitable crypto-system form resource-constraint devices

Modelagem e projeto de conversores AC/DC de ultrabaixa tensão de operação

Tese (doutorado) - Universidade Federal de Santa Catarina, Centro Tecnológico. Programa de Pós-Graduação em Engenharia ElétricaEsta tese apresenta o desenvolvimento de um modelo analítico e muito simples do circuito retificador, considerando a lei corrente-tensão (exponencial) do diodo, tendo como mérito simplificar um problema relativamente complexo e não linear (retificador) com uma ótima precisão. O modelo mostra-se válido, mesmo para tensões abaixo da tensão térmica, tendo sido testado para um ampla variação de tensão e corrente. São apresentadas equações para a tensão DC de saída, ripple de tensão, transiente durante o startup e eficiência de conversão de potência. Para validação, o modelo é comparado à simulações realizadas em simulador SPICE e a resultados experimentais, mostrando uma ótima precisão. Comparando-se este modelo com outros citados nas referências bibliográficas, este possui a vantagem de ser analítico, mais simples e/ou mais preciso. O desenvolvimento deste modelo torna-se mais importante, à medida que cresce o interesse pela utilização de sensores remotos autoalimentados, e também pelo uso de dispositivos de identificação por rádiofrequência (RFID). O espaço de projeto do conversor AC/DC foi explorado por meio de equações simples e de uma metodologia de projeto desenvolvida para que, através de gráficos, o projetista possa de forma fácil, rápida e com boa precisão, determinar os principais elementos do conversor AC/DC e da rede de adaptação de impedâncias. Para alcançar potências menores na entrada do conversor AC/DC, a metodologia utiliza redes de adaptação de impedâncias para o casamento entre as impedâncias da antena (ou impedância da fonte geradora de sinal AC) e do conversor AC/DC. Além disso, esta metodologia pode ser utilizada para conversores AC/DC com diodos ou transistores conectados como diodos, mesmo que sua equação característica não seja a do diodo exponencial. Para a utilização do conversor AC/DC em circuitos integrados, são estudadas as possibilidades de uso do transistor MOS conectado como diodo operando na região de inversão fraca. Para obter suporte experimental, foram projetados multiplicadores de tensão, com rede de adaptação de impedâncias incorporada ao circuito integrado e também externa ao mesmo, com o objetivo de atingir a menor potência de entrada disponível.This thesis presents a simple analytical model of the rectifier circuit assuming that the diode is characterized by the exponential current-voltage law. The model shown is valid even for voltages below the thermal voltage and it has been tested for a wide range of voltages and currents. Equations are provided for the DC output voltage, ripple voltage, transient during startup and power conversion efficiency. For validation, the model is compared to simulations carried out in SPICE and experimental results, showing a good accuracy. Comparing this model with others cited in the references, this one has the advantage of being analytical, simpler, and more accurate. The development of this model becomes more relevant with the growing use of self powered remote sensors, and radio frequency identification devices (RFID). The design space of the AC/DC converter was explored using a graphic methodology. To operate with reduced power at the input, the methodology uses an impedance adaptation network for the matching between the impedances of the antenna (or the source impedance of the AC signal) and that of the AC/DC converter. Furthermore, this methodology can be used for AC/DC converters with diodes or transistors connected as diodes, even if their characteristic equations are not exponential. To obtain experimental support, voltage multipliers have been designed with impedance adaptation network incorporated into the integrated circuit and also external to it, in order to achieve the lowest possible power at the input