4 research outputs found
Energy reduction in 3D NoCs through communication optimization
Cataloged from PDF version of article.Network-on-Chip (NoC) architectures and three-dimensional (3D) integrated circuits have been introduced as attractive options for overcoming the barriers in interconnect scaling while increasing the number of cores. Combining these two approaches is expected to yield better performance and higher scalability. This paper explores the possibility of combining these two techniques in a heterogeneity aware fashion. Specifically, on a heterogeneous 3D NoC architecture, we explore how different types of processors can be optimally placed to minimize data access costs. Moreover, we select the optimal set of links with optimal voltage levels. The experimental results indicate significant savings in energy consumption across a wide range of values of our major simulation parameters
Energy reduction in 3D NoCs through communication optimization
Network-on-Chip (NoC) architectures and three-dimensional (3D) integrated circuits have been introduced as attractive options for overcoming the barriers in interconnect scaling while increasing the number of cores. Combining these two approaches is expected to yield better performance and higher scalability. This paper explores the possibility of combining these two techniques in a heterogeneity aware fashion. Specifically, on a heterogeneous 3D NoC architecture, we explore how different types of processors can be optimally placed to minimize data access costs. Moreover, we select the optimal set of links with optimal voltage levels. The experimental results indicate significant savings in energy consumption across a wide range of values of our major simulation parameters. © 2013, Springer-Verlag Wien
Design of Networks on Chips for 3D ICs
Three-dimensional integrated circuits, where multiple
silicon layers are stacked vertically have emerged
recently. The3DICs have smaller form factor, shorter
and efficient use of wires and allow integration of diverse
technologies in the same device. The use of
Networks on Chips (NoCs) to connect components in a
3D chip is a necessity. In this short paper, we present
an outline on designing application-specific NoCs
for 3D ICs