A Scalable Correlator Architecture Based on Modular FPGA Hardware, Reuseable Gateware, and Data Packetization

A new generation of radio telescopes is achieving unprecedented levels of sensitivity and resolution, as well as increased agility and field-of-view, by employing high-performance digital signal processing hardware to phase and correlate large numbers of antennas. The computational demands of these imaging systems scale in proportion to BMN^2, where B is the signal bandwidth, M is the number of independent beams, and N is the number of antennas. The specifications of many new arrays lead to demands in excess of tens of PetaOps per second. To meet this challenge, we have developed a general purpose correlator architecture using standard 10-Gbit Ethernet switches to pass data between flexible hardware modules containing Field Programmable Gate Array (FPGA) chips. These chips are programmed using open-source signal processing libraries we have developed to be flexible, scalable, and chip-independent. This work reduces the time and cost of implementing a wide range of signal processing systems, with correlators foremost among them,and facilitates upgrading to new generations of processing technology. We present several correlator deployments, including a 16-antenna, 200-MHz bandwidth, 4-bit, full Stokes parameter application deployed on the Precision Array for Probing the Epoch of Reionization.Comment: Accepted to Publications of the Astronomy Society of the Pacific. 31 pages. v2: corrected typo, v3: corrected Fig. 1

The Analogue Computer as a Voltage-Controlled Synthesiser

This paper re-appraises the role of analogue computers within electronic and computer music and provides some pointers to future areas of research. It begins by introducing the idea of analogue computing and placing in the context of sound and music applications. This is followed by a brief examination of the classic constituents of an analogue computer, contrasting these with the typical modular voltage-controlled synthesiser. Two examples are presented, leading to a discussion on some parallels between these two technologies. This is followed by an examination of the current state-of-the-art in analogue computation and its prospects for applications in computer and electronic music

Hardware for digitally controlled scanned probe microscopes

The design and implementation of a flexible and modular digital control and data acquisition system for scanned probe microscopes (SPMs) is presented. The measured performance of the system shows it to be capable of 14-bit data acquisition at a 100-kHz rate and a full 18-bit output resolution resulting in less than 0.02-Å rms position noise while maintaining a scan range in excess of 1 µm in both the X and Y dimensions. This level of performance achieves the goal of making the noise of the microscope control system an insignificant factor for most experiments. The adaptation of the system to various types of SPM experiments is discussed. Advances in audio electronics and digital signal processors have made the construction of such high performance systems possible at low cost

Current and Nascent SETI Instruments

Here we describe our ongoing efforts to develop high-performance and sensitive instrumentation for use in the search for extra-terrestrial intelligence (SETI). These efforts include our recently deployed Search for Extraterrestrial Emissions from Nearby Developed Intelligent Populations Spectrometer (SERENDIP V.v) and two instruments currently under development; the Heterogeneous Radio SETI Spectrometer (HRSS) for SETI observations in the radio spectrum and the Optical SETI Fast Photometer (OSFP) for SETI observations in the optical band. We will discuss the basic SERENDIP V.v instrument design and initial analysis methodology, along with instrument architectures and observation strategies for OSFP and HRSS. In addition, we will demonstrate how these instruments may be built using low-cost, modular components and programmed and operated by students using common languages, e.g. ANSI C.Comment: 12 pages, 5 figures, Original version appears as Chapter 2 in "The Proceedings of SETI Sessions at the 2010 Astrobiology Science Conference: Communication with Extraterrestrial Intelligence (CETI)," Douglas A. Vakoch, Edito

FPGA design methodology for industrial control systems—a review

This paper reviews the state of the art of fieldprogrammable gate array (FPGA) design methodologies with a focus on industrial control system applications. This paper starts with an overview of FPGA technology development, followed by a presentation of design methodologies, development tools and relevant CAD environments, including the use of portable hardware description languages and system level programming/design tools. They enable a holistic functional approach with the major advantage of setting up a unique modeling and evaluation environment for complete industrial electronics systems. Three main design rules are then presented. These are algorithm refinement, modularity, and systematic search for the best compromise between the control performance and the architectural constraints. An overview of contributions and limits of FPGAs is also given, followed by a short survey of FPGA-based intelligent controllers for modern industrial systems. Finally, two complete and timely case studies are presented to illustrate the benefits of an FPGA implementation when using the proposed system modeling and design methodology. These consist of the direct torque control for induction motor drives and the control of a diesel-driven synchronous stand-alone generator with the help of fuzzy logic

MFPA: Mixed-Signal Field Programmable Array for Energy-Aware Compressive Signal Processing

Compressive Sensing (CS) is a signal processing technique which reduces the number of samples taken per frame to decrease energy, storage, and data transmission overheads, as well as reducing time taken for data acquisition in time-critical applications. The tradeoff in such an approach is increased complexity of signal reconstruction. While several algorithms have been developed for CS signal reconstruction, hardware implementation of these algorithms is still an area of active research. Prior work has sought to utilize parallelism available in reconstruction algorithms to minimize hardware overheads; however, such approaches are limited by the underlying limitations in CMOS technology. Herein, the MFPA (Mixed-signal Field Programmable Array) approach is presented as a hybrid spin-CMOS reconfigurable fabric specifically designed for implementation of CS data sampling and signal reconstruction. The resulting fabric consists of 1) slice-organized analog blocks providing amplifiers, transistors, capacitors, and Magnetic Tunnel Junctions (MTJs) which are configurable to achieving square/square root operations required for calculating vector norms, 2) digital functional blocks which feature 6-input clockless lookup tables for computation of matrix inverse, and 3) an MRAM-based nonvolatile crossbar array for carrying out low-energy matrix-vector multiplication operations. The various functional blocks are connected via a global interconnect and spin-based analog-to-digital converters. Simulation results demonstrate significant energy and area benefits compared to equivalent CMOS digital implementations for each of the functional blocks used: this includes an 80% reduction in energy and 97% reduction in transistor count for the nonvolatile crossbar array, 80% standby power reduction and 25% reduced area footprint for the clockless lookup tables, and roughly 97% reduction in transistor count for a multiplier built using components from the analog blocks. Moreover, the proposed fabric yields 77% energy reduction compared to CMOS when used to implement CS reconstruction, in addition to latency improvements