A thermally aware performance analysis of quantum cellular automata logic gates

The high-performance digital circuits can be constructed at high operating frequency, reduced power dissipation, portability, and large density. Using conventional complementary-metal-oxide-semiconductor (CMOS) design process, it is quite difficult to achieve ultra-high-speed circuits due to scaling problems. Recently quantum dot cellular automata (QCA) are prosed to develop logic circuits at atomic level. In this paper, we analyzed the performance of QCA circuits under different temperature effects and observed that polarization of the cells is highly sensitive to temperature. In case of the 3-input majority gate the cell polarization drops to 50% with an increase in the temperature of 18 K and for 5 input majority gate the cell polarization drops more quickly than the 3-input majority. Further, the performance of majority gates also compared in terms of area and power dissipation. It has been noticed that the proposed logic gates can also be used for developing simple and complex and memory circuits

Robust QCA Full Adders Using a Novel Fault Tolerant Five-Input Majority Gate

A novel technique for creating logic gates and digital circuitry at the nanoscale is quantum cellular automata (QCA). The sensitivity of the circuit is enhanced and quantum circuits are more susceptible to unfavorable external conditions when component size are reduced. In this article, we offer a five-input majority gate with fault-tolerant feature in QCA technology, taking into account the significance of constructing circuits that can withstand flaws. We also assess all potential defects in the process of arranging cells in specific locations on the surface. These errors consist of extra cells, rotation, deletion, and displacement. The gate under study is subjected to the aforementioned four failure categories in the first stage. The QCADesigner simulator engine is then used to assess the accuracy of the circuit performance in the second step. 41 quantum cells have been used to make the gate of this five-input majority gate with fault-tolerant feature in QCA technology. Several techniques are explored to discover such a majority gate, such as adding cells (i.e., introducing redundancy into the circuit) and particular cell layout techniques. The goal is to come up with a design that can ideally withstand possible faults with the least amount of overhead on the circuit for fault-tolerant through a certain cell layout. The findings demonstrate the implemented majority gate's notable advantage over comparable scenarios