Gaussian filtering for FPGA based image processing with High-Level Synthesis tools

With the gradual improvement and uprising interest from the industry to High-Level Synthesis tools, like Vivado HLS form Xilinx, Field Programmable Gate Arrays are becoming an attractive option for accelerator architecture in image processing domain. However, an efficient high-level design still requires knowledge of hardware specifics. A great amount of image processing operations falls into a group of convolution-based operators - operators which result depends only on a particular pixel and its neighborhood and obtained by performing a convolution between a kernel and a part of an image. This paper investigates the impact of factors, such as kernel size, target frequency, convolution implementation specifics, floating-point vs. fixed-point filter kernel, on resulting register-transfer level design of convolution-based operators and FPGA resources utilization. The Gaussian filter was analyzed as an example of a convolution-based operator. It is shown experimentally that floating-point operators require a noticeably larger amount of resources, rather fixed-point once. Resulting clock frequency independence from kernel size is demonstrated as well as the number of used flip-flops grows with the increasing target clock frequency is investigated in this work.Although using of HLS can simplify and accelerates the development of FPGA-based applications, it is still requires careful design space exploration. It is crucial to remember that existing HLS tools do not provide full abstraction and the result of the development is not software but hardware. The efficiency of resulting FPGA solution and its resources utilization depends heavily on many factors which have to be taken into account on the programming stage. Floating-point operations implemented on FPGA are usually inefficient and consume a tremendous amount of resources, therefore should be avoided. Kernel size doesn’t affect clock frequency and just increases the number of resources required for storing bigger kernel and temporary image areas. A number of used flip-flops grows rapidly with the increasing target clock frequency and generally bigger for bigger kernels. Therefore a trade-off between target speed and resources utilization should be considered by a developer. A benefit achieved with the use of vendor-provided libraries has to be noted. They provide convenient abstractions usually at no additional resources cost. Thus, for instance, window and line buffers from Vivado Video Library might be used as an alternative to hand-programmed data structures. Results obtained in this work might be extended to any convolution-based image processing operator implemented on FPGA with HLS

Sviluppo e realizzazione di un circuito di controllo per la gestione di un modulo di visione hd miniaturizzato per colonscopia

La seguente tesi ha come oggetto la progettazione di un sistema per il controllo e il testing di un sensore di immagine disegnato ad hoc per la colonscopia, l’EYE-TECH1080 e di un chip companion, l’EYE-TECH_DigitalOut, recentemente sviluppati dall’azienda EYE-TECH s.r.l., Spin-Off della Scuola Superiore Sant’Anna. L’azienda ha commissionato tale sistema al fine di eseguire la caratterizzazione ottica ed elettronica dei loro prodotti al fine di testarne le performance e di massimizzarle modificando taluni parametri elettrici, prima di immettere tali chip sul mercato. Scopo della tesi è stato pertanto il design, lo sviluppo e il test di una scheda elettronica che inglobasse il sensore d’immagine e il chip companion e tutta la componentistica elettronica necessaria. In particolare il sistema realizzato è composto da due schede impilate: un development kit della Lattice Semiconductor provvisto di protocollo di comunicazione USB 2.0 High-Speed, memorie SRAM DDR3 ed FPGA per la gestione dell’intero sistema ed una scheda custom, oggetto della tesi, in grado di interfacciarsi con il development kit. Tale scheda è stata progettata al fine di consentire la massima flessibilità operativa, garantendo più configurazioni del sistema. Tematiche di riduzione del rumore e predisposizione per una futura miniaturizzazione sono state prese in considerazione durante la fase di progettazione. Test elettrici preliminari sono stati effettuati sull'intero sistema per verificare la correttezza del design, sono inoltre state verifficate che tutte le specifiche richieste dall'azienda siano state implementate

Design of an imaging system based on FPGA technology and CMOS imager

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