The design and multiplier-less realization of software radio receivers with reduced system delay

This paper studies the design and multiplier-less realization of a new software radio receiver (SRR) with reduced system delay. It employs low-delay finite-impulse response (FIR) and digital allpass filters to effectively reduce the system delay of the multistage decimators in SRRs. The optimal least-square and minimax designs of these low-delay FIR and allpass-based filters are formulated as a semidefinite programming (SDP) problem, which allows zero magnitude constraint at ω = π to be incorporated readily as additional linear matrix inequalities (LMIs). By implementing the sampling rate converter (SRC) using a variable digital filter (VDF) immediately after the integer decimators, the needs for an expensive programmable FIR filter in the traditional SRR is avoided. A new method for the optimal minimax design of this VDF-based SRC using SDP is also proposed and compared with traditional weight least squares method. Other implementation issues including the multiplier-less and digital signal processor (DSP) realizations of the SRR and the generation of the clock signal in the SRC are also studied. Design results show that the system delay and implementation complexities (especially in terms of high-speed variable multipliers) of the proposed architecture are considerably reduced as compared with conventional approaches. © 2004 IEEE.published_or_final_versio

Variable fractional delay filter with sub-expression coefficients

Variable fractional delay (VFD) filters are useful for various signal processing and communication applications with frequency characteristics such as fractional delays to be varied online. In this paper, we investigate the design of VFD filters with discrete coefficients as a means of achieving low complexity and efficient hardware implementation. The optimization problem with minimax criterion is formulated as a mixed integer programming problem with a non-linear cost function and continuous constraints. An efficient optimization procedure is proposed to tackle the design problem that includes a combination of the branch and bound method and an adaptive scheme for discretization. Design examples are given to demonstrate the effectiveness of the proposed algorithm

A study of optimization and optimal control computation : exact penalty function approach

In this thesis, We propose new computational algorithms and methods for solving four classes of constrained optimization and optimal control problems. In Chapter 1, we present a brief review on optimization and optimal control. In Chapter 2, we consider a class of continuous inequality constrained optimization problems. The continuous inequality constraints are first approximated by smooth function in integral form. Then, we construct a new exact penalty function, where the summation of all these approximate smooth functions in integral form, called the constraint violation, is appended to the objective function. In this way, we obtain a sequence of approximate unconstrained optimization problems. It is shown that if the value of the penalty parameter is sufficiently large, then any local minimizer of the corresponding unconstrained optimization problem is a local minimizer of the original problem. For illustration, three examples are solved using the proposed method.From the solutions obtained, we observe that the values of their objective functions are amongst the smallest when compared with those obtained by other existing methods available in the literature. More importantly, our method finds solutions which satisfy the continuous inequality constraints.In Chapter 3, we consider a general class of nonlinear mixed discrete programming problems. By introducing continuous variables to replace the discrete variables, the problem is first transformed into an equivalent nonlinear continuous optimization problem subject to original constraints and additional linear and quadratic constraints. However, the existing gradient-based optimization techniques have difficulty to solve this equivalent nonlinear optimization problem effectively due to the new quadratic inequality constraint. Thus, an exact penalty function is employed to construct a sequence of unconstrained optimization problems, each of which can be solved effectively by unconstrained optimization techniques, such as conjugate gradient or quasi-Newton types of methods.It is shown that any local optimal solution of the unconstrained optimization problem is a local optimal solution of the transformed nonlinear constrained continuous optimization problem when the penalty parameter is sufficiently large. Numerical experiments are carried out to test the efficiency of the proposed method.In Chapter 4, we investigate the optimal design of allpass variable fractional delay (VFD) filters with coefficients expressed as sums of signed powers-of-two terms, where the weighted integral squared error is minimized. A new optimization procedure is proposed to generate a reduced discrete search region. Then, a new exact penalty function method is developed to solve the optimal design of allpass variable fractional delay filter with signed powers-of-two coefficients. Design examples show that the proposed method is highly effective. Compared with the conventional quantization method, the solutions obtained by our method are of much higher accuracy. Furthermore, the computational complexity is low.In Chapter 5, we consider an optimal control problem in which the control takes values from a discrete set and the state and control are subject to continuous inequality constraints. By introducing auxiliary controls and applying a time-scaling transformation, we transform this optimal control problem into an equivalent optimal control problem subject to original constraints and additional linear and quadratic constraints, where the decision variables are taking values from a feasible region, which is the union of some continuous sets. However, due to the new quadratic constraints, standard optimization techniques do not perform well when they are applied to solve the transformed problem directly.We introduce a novel exact penalty function to penalize constraint violations, and then append this penalty function to the objective function, forming a penalized objective function. This leads to a sequence of approximate optimal control problems, each of which can be solved by using optimal control techniques, and consequently, many optimal control software packages, such as MISER 3.4, can be used. Convergence results how that when the penalty parameter is sufficiently large, any local solution of the approximate problem is also a local solution of the original problem. We conclude this chapter with some numerical results for two train control problems.In Chapter 6, some concluding remarks and suggestions for future research directions are made

Digital Filters

The new technology advances provide that a great number of system signals can be easily measured with a low cost. The main problem is that usually only a fraction of the signal is useful for different purposes, for example maintenance, DVD-recorders, computers, electric/electronic circuits, econometric, optimization, etc. Digital filters are the most versatile, practical and effective methods for extracting the information necessary from the signal. They can be dynamic, so they can be automatically or manually adjusted to the external and internal conditions. Presented in this book are the most advanced digital filters including different case studies and the most relevant literature

On the design and efficient implementation of the Farrow structure

This letter proposes an efficient implementation of the Farrow structure using sum-of-powers-of-two (SOPOT) coefficients and multiplier-block (MB). In particular, a novel algorithm for designing the Farrow coefficients in SOPOT form is detailed. Using the SOPOT coefficient representation, coefficient multiplication can be implemented with limited number of shifts and additions. Using MB, the redundancy between multipliers can be fully exploited through the reuse of the intermediate results generated. Design examples show that the proposed method can greatly reduce the complexity of the Farrow structure while providing comparable phase and amplitude responses.published_or_final_versio

Digital Filters and Signal Processing

Digital filters, together with signal processing, are being employed in the new technologies and information systems, and are implemented in different areas and applications. Digital filters and signal processing are used with no costs and they can be adapted to different cases with great flexibility and reliability. This book presents advanced developments in digital filters and signal process methods covering different cases studies. They present the main essence of the subject, with the principal approaches to the most recent mathematical models that are being employed worldwide

FPGA Implementation of the Front-End of a DOCSIS 3.0 Receiver

The introduction of cable television (CATV) in the 1940s and 1950s has significantly influenced communications technology. Originally supplying only one-way television programming, the CATV industry recognized the potential of two-way communications. Starting with the introduction of pay-per view services in the 1980s, two-way communications over CATV networks eventually expanded into supplying internet access services. The increased demand for CATV services, and thus the increased demand for CATV equipment, has led the CATV industry to develop interoperability standards. The primary standard now used by the CATV industry is the Data Over Cable Service Specification (DOCSIS). DOCSIS defines both the upstream (data towards the CATV provider) and downstream (data towards the CATV customer) transmission channels. This includes specifications for the modulators and demodulators used in these channels. The number of manufacturers of CATV modulators and demodulators has greatly increased over the last twenty years and continues to do so. As the number of competitive CATV equipment suppliers increases, these manufacturers must look to ways to remain competitive by reducing time-to-market and costs associated with equipment design, as well as allowing their designs to be flexible so that they may adapt to the improvements in DOCSIS. In the past, manufacturers have primarily used Application Specific Integrated Circuits (ASICs) to implement digital hardware designs for CATV equipment. ASICs have a very high initial setup cost and do not allow for system modifications without a complete redesign. Recently, Field Programmable Gate Array (FPGA) technology has been introduced that allows manufacturers to both modify their designed digital hardware structures without a complete physical hardware redesign, as well as providing a reduced initial setup cost. Although in the long term, ASICs provide a cheaper alternative to FPGAs when produced in quantity, FPGAs provide quicker time-to-market in new product development and allow changes to made after initial release. This ability to change designs after release and the quicker time-to-market has led manufacturers to adopt FPGAs in new products. A critical component in the upstream channel of a DOCSIS compliant system is the Quadrature Amplitude Modulated (QAM) receiver. The data received at the QAM receiver have undergone several impairments including additive noise, timing offset, and frequency and phase mismatches between the transmitted modulated signal and the signal received at the demodulator. It is the function of the front-end of the receiver to correct for these impairments. This thesis presents methods for, and an example of, the design and implementation of a DOCSIS compliant QAM receiver front-end that corrects for timing, phase and frequency impairments experienced in the upstream communication channel when additive noise is present. The circuits presented are designed and implemented to reduce hardware costs when using FPGA technology. In addition, the circuits designed do not use proprietary logic, which gives designers more flexibility when implementing their own demodulator front-end circuitry. The FPGA implementation presented in this thesis achieves an average MER of 54.3 dB in a no-noise channel and close to 31 dB MER in a 25 dBc AWGN channel. The overall design uses 65 dedicated 18-bit by 18-bit multipliers and 2,970 bytes of RAM to implement the digital front-end of the receiver

Design and Implementation of Complexity Reduced Digital Signal Processors for Low Power Biomedical Applications

Wearable health monitoring systems can provide remote care with supervised, inde-pendent living which are capable of signal sensing, acquisition, local processing and transmission. A generic biopotential signal (such as Electrocardiogram (ECG), and Electroencephalogram (EEG)) processing platform consists of four main functional components. The signals acquired by the electrodes are amplified and preconditioned by the (1) Analog-Front-End (AFE) which are then digitized via the (2) Analog-to-Digital Converter (ADC) for further processing. The local digital signal processing is usually handled by a custom designed (3) Digital Signal Processor (DSP) which is responsible for either anyone or combination of signal processing algorithms such as noise detection, noise/artefact removal, feature extraction, classification and compres-sion. The digitally processed data is then transmitted via the (4) transmitter which is renown as the most power hungry block in the complete platform. All the afore-mentioned components of the wearable systems are required to be designed and fitted into an integrated system where the area and the power requirements are stringent. Therefore, hardware complexity and power dissipation of each functional component are crucial aspects while designing and implementing a wearable monitoring platform. The work undertaken focuses on reducing the hardware complexity of a biosignal DSP and presents low hardware complexity solutions that can be employed in the aforemen-tioned wearable platforms. A typical state-of-the-art system utilizes Sigma Delta (Σ∆) ADCs incorporating a Σ∆ modulator and a decimation filter whereas the state-of-the-art decimation filters employ linear phase Finite-Impulse-Response (FIR) filters with high orders that in-crease the hardware complexity [1–5]. In this thesis, the novel use of minimum phase Infinite-Impulse-Response (IIR) decimators is proposed where the hardware complexity is massively reduced compared to the conventional FIR decimators. In addition, the non-linear phase effects of these filters are also investigated since phase non-linearity may distort the time domain representation of the signal being filtered which is un-desirable effect for biopotential signals especially when the fiducial characteristics carry diagnostic importance. In the case of ECG monitoring systems the effect of the IIR filter phase non-linearity is minimal which does not affect the diagnostic accuracy of the signals. The work undertaken also proposes two methods for reducing the hardware complexity of the popular biosignal processing tool, Discrete Wavelet Transform (DWT). General purpose multipliers are known to be hardware and power hungry in terms of the number of addition operations or their underlying building blocks like full adders or half adders required. Higher number of adders leads to an increase in the power consumption which is directly proportional to the clock frequency, supply voltage, switching activity and the resources utilized. A typical Field-Programmable-Gate-Array’s (FPGA) resources are Look-up Tables (LUTs) whereas a custom Digital Signal Processor’s (DSP) are gate-level cells of standard cell libraries that are used to build adders [6]. One of the proposed methods is the replacement of the hardware and power hungry general pur-pose multipliers and the coefficient memories with reconfigurable multiplier blocks that are composed of simple shift-add networks and multiplexers. This method substantially reduces the resource utilization as well as the power consumption of the system. The second proposed method is the design and implementation of the DWT filter banks using IIR filters which employ less number of arithmetic operations compared to the state-of-the-art FIR wavelets. This reduces the hardware complexity of the analysis filter bank of the DWT and can be employed in applications where the reconstruction is not required. However, the synthesis filter bank for the IIR wavelet transform has a higher computational complexity compared to the conventional FIR wavelet synthesis filter banks since re-indexing of the filtered data sequence is required that can only be achieved via the use of extra registers. Therefore, this led to the proposal of a novel design which replaces the complex IIR based synthesis filter banks with FIR fil-ters which are the approximations of the associated IIR filters. Finally, a comparative study is presented where the hybrid IIR/FIR and FIR/FIR wavelet filter banks are de-ployed in a typical noise reduction scenario using the wavelet thresholding techniques. It is concluded that the proposed hybrid IIR/FIR wavelet filter banks provide better denoising performance, reduced computational complexity and power consumption in comparison to their IIR/IIR and FIR/FIR counterparts

On the design and implementation of FIR and IIR digital filters with variable frequency characteristics

This paper studies the design and implementation of finite-impulse response (FIR) and infinite-impulse response (IIR) variable digital filters (VDFs), whose frequency characteristics can be controlled continuously by some control or tuning parameters. A least squares (LS) approach is proposed for the design of FIR VDFs by expressing the impulse response of the filter as a linear combination of basis functions. It is shown that the optimal LS solution can be obtained by solving a system of linear equations. By choosing the basis functions as piecewise polynomials, VDFs with larger tuning range than that of ordinary polynomial based approach results. The proposed VDF can be efficiently implemented using the familiar Farrow structure. Making use of the FIR VDF so obtained, an Eigensystem Realization Algorithm (ERA)-based model reduction technique is proposed to approximate the FIR VDF by a stable IIR VDF with lower system order. The advantages of the model reduction approach are: 1) it is computational simple which only requires the computation of the singular value decomposition of a Hankel matrix; 2) the IIR VDF obtained is guaranteed to be stable; and 3) the frequency response such as the phase response of the FIR prototype is well preserved. Apart from the above advantages, the proposed IIR VDF does not suffer from undesirable transient response during parameter tuning found in other approaches based on direct tuning of filter parameters. For frequency selective VDFs, about 40% of the multiplications can be saved using the IIR VDFs. The implementation of the proposed FIR VDF using sum-of-powers-of-two (SOPOT) coefficient and the multiplier block (MB) technique are also studied. Results show that about two-third of the additions in implementing the multiplication of the SOPOT coefficients can be saved using the multiplier block, which leads to significant savings in hardware complexity.link_to_subscribed_fulltex

Design of quadrature mirror filter banks with canonical signed digit coefficients using genetic algorithms.

This thesis is about the use of a genetic algorithm to design QMF bank with canonical signed digit coefficients. A filter bank has applications in areas like video and audio coding, data communication, etc. Filter bank design is a multiobjective optimization problem. The performance depends on the reconstruction error of the overall filter bank and the individual performance of the composing lowpass filter. In this thesis we have used reconstruction error of the overall filter bank as our main objective and passband error, stopband error, stopband and passband ripples and transition width of the individual lowpass filter as constraints. Therefore filter bank design can be formulated as single objective multiple constraint optimization problem. A unique genetic algorithm is developed to optimize filer bank coefficients such that the corresponding system\u27s response matches that of an ideal system with an additional constraint that all coefficients are in canonical signed digit (CSD) format. A special restoration technique is used to restore the CSD format of the coefficients after crossover and mutation operators in Genetic algorithm. The proposed restoration technique maintains the specified word length and the maximum number of nonzero digits in filter banks coefficients. Experimental results are presented at the end. It is demonstrated that the designed genetic algorithm is reliable, and efficient for designing QMF banks.Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis2004 .U67. Source: Masters Abstracts International, Volume: 43-05, page: 1785. Thesis (M.A.Sc.)--University of Windsor (Canada), 2004