Frequency and Pulse Generation Features in a Multifunctional Field Calibrator

The aim of the Thesis was to investigate improvements that could be made for frequency and pulse generation features of a next-generation multifunctional field calibrator as well as to suggests how the found improvements could be implemented. The improvement investigation was done by reviewing the frequency and pulse generation specifications of multifunctional calibrators that were on the market during the writing process of the Thesis. In addition to that, a customer needs analysis was performed by interviewing experts, and by analyzing customers’ feedback. Based on the results of the investigation, it can be concluded that the frequency and amplitude range and resolution of the current solution by Beamex is competitive and do not require alternation. However, the selection of generatable waveforms could be improved by adding a sine wave generation possibility into the frequency generation function. The current solution is only capable of generating symmetric and positive square waves. Furthermore, some requests for dual pulse generation were found during the investigation. The main focus in the solution design process was the sine wave generation because the dual pulse generation can be utilized easily if the next-generation multifunctional field calibrator has a modular structure. In that case, the number of frequency and pulse generation channels in the calibrator can be increased by adding multiple frequency and pulse generation modules into the calibrator. On the other hand, adding a sine wave generation option to the system is more complicated. Two possible solution suggestions for sine wave generation were designed and evaluated in the present thesis. One solution is based on direct digital synthesis and another one on usage of timer, registers, and direct memory access feature of a microcontroller. In theory, both of the solution suggestions should be able to generate square, pulse, and sine waves. However, by evaluating the solution suggestions, it can be said that the option to generate sine waves increases the complexity and cost of the system. In addition to that, the demand for sine wave generation might not be that high. Hence, it should be re-evaluated if it is profitable to add a sine wave option to the frequency generation

Design Techniques for High-Performance SAR A/D Converters

The design of electronics needs to account for the non-ideal characteristics of the device technologies used to realize practical circuits. This is particularly important in mixed analog-digital design since the best device technologies are very different for digital compared to analog circuits. One solution for this problem is to use a calibration correction approach to remove the errors introduced by devices, but this adds complexity and power dissipation, as well as reducing operation speed, and so must be optimised. This thesis addresses such an approach to improve the performance of certain types of analog-to-digital converter (ADC) used in advanced telecommunications, where speed, accuracy and power dissipation currently limit applications. The thesis specifically focuses on the design of compensation circuits for use in successive approximation register (SAR) ADCs. ADCs are crucial building blocks in communication systems, in general, and for mobile networks, in particular. The recently launched fifth generation of mobile networks (5G) has required new ADC circuit techniques to meet the higher speed and lower power dissipation requirements for 5G technology. The SAR has become one of the most favoured architectures for designing high-performance ADCs, but the successive nature of the circuit operation makes it difficult to reach ∼GS/s sampling rates at reasonable power consumption. Here, two calibration techniques for high-performance SAR ADCs are presented. The first uses an on-chip stochastic-based mismatch calibration technique that is able to accurately compute and compensate for the mismatch of a capacitive DAC in a SAR ADC. The stochastic nature of the proposed calibration method enables determination of the mismatch of the CAPDAC with a resolution much better than that of the DAC. This allows the unit capacitor to scale down to as low as 280aF for a 9-bit DAC. Since the CAP-DAC causes a large part of the overall dynamic power consumption and directly determines both the sizes of the driving and sampling switches and the size of the input capacitive load of the ADC and the kT/C noise power, a small CAP-DAC helps the power efficiency. To validate the proposed calibration idea, a 10-bit asynchronous SAR ADC was fabricated in 28-nm CMOS. Measurement results show that the proposed stochastic calibration improves the ADC’s SFDR and SNDR by 14.9 dB, 11.5 dB, respectively. After calibration, the fabricated SAR ADC achieves an ENOB of 9.14 bit at a sampling rate of 85 MS/s, resulting in a Walden FoM of 10.9 fJ/c-s. The second calibration technique is a timing-skew calibration for a time-interleaved (TI) SAR ADC that calibrates/computes the inter-channel timing and offset mismatch simultaneously. Simulation results show the effectiveness of this calibration method. When used together, the proposed mismatch calibration technique and the timing-skew calibration technique enables a TI SAR ADC to be designed that can achieve a sampling rate of ∼GS/s with 10-bit resolution and a power consumption as low as ∼10mW; specifications that satisfy the requirements of 5G technology

Design of a sinusoidal signal generator with calibrated harmonic cancellation for mixed-signal BIST in a 28 nm FDSOI technology

International audienceThis work presents the design of a high-frequency on-chip sinusoidal signal generator based on a calibrated har- monic cancellation strategy. The proposed generator employs a digital shift-register to provide a set of phase-shifted digital square-wave signals. These square-wave signals are scaled and combined using a harmonic cancellation strategy in a simplified current-steering DAC with only five branches. The proposed architecture allows the cancellation of all harmonic components up to the eleventh. Additionally, a simple calibration strategy has been devised to compensate the impact of process variations and mismatch on the effectiveness of the harmonic cancellation. The simplicity of the circuitry makes this approach suitable for mixed-signal BIST applications. Electrical simulations of a 28 nm FDSOI design are provided to validate the functionality of the proposed signal generator. Obtained results show a calibrated performance around 70 dB of SFDR for a generated sinusoidal signal at 166 MHz