Variation Resilient Adaptive Controller for Subthreshold Circuits

Subthreshold logic is showing good promise as a viable ultra-low-power circuit design technique for power-limited applications. For this design technique to gain widespread adoption, one of the most pressing concerns is how to improve the robustness of subthreshold logic to process and temperature variations. We propose a variation resilient adaptive controller for subthreshold circuits with the following novel features: new sensor based on time-to-digital converter for capturing the variations accurately as digital signatures, and an all-digital DC-DC converter incorporating the sensor capable of generating an operating operating Vdd from 0V to 1.2V with a resolution of 18.75mV, suitable for subthreshold circuit operation. The benefits of the proposed controller is reflected with energy improvement of up to 55% compared to when no controller is employed. The detailed implementation and validation of the proposed controller is discussed

1 V CMOS subthreshold log domain PDM

A new CMOS circuit strategy for very low-voltage Pulse-Duration Modulators (PDM) is proposed. Optimization of voltage supply scaling below the sum of threshold voltages is based on Instantaneous Log Companding processing through the MOSFET operating in weak inversion. A 1 V VLSI PDM circuit for very low-voltage audio applications such as Hearing Aids is presented, showing good agreement between simulated and experimental data.Comisión Interministerial de Ciencia y Tecnología TIC97-1159, TIC99-1084European Union 2306

A Novel Cyclic Time to Digital Converter Based on Triple-Slope Interpolation and Time Amplification

This paper investigates a novel cyclic time-to-digital converter (TDC) which employs triple-slope analog interpolation and time amplification techniques for digitizing the time interval between the rising edges of two input signals(Start and Stop). The proposed converter will be a 9-bit cyclic time-to-digital converter that does not use delay lines in its structure. Therefore, it has a low sensitivity to temperature, power supply and process (PVT) variations. The other advantages of the proposed converter are low circuit complexity, and high accuracy compared with the time-to-digital converters that have previously been proposed. Also, this converter improves the time resolution and the dynamic range. In the same resolution, linear range and dynamic range, the proposed cyclic TDC reduces the number of circuit elements compared with the converters that have a similar circuit structure. Thus, the converter reduces the chip area, the power consumption and the figure of merit (FoM). In this converter, the integral nonlinearity (INL) and differential nonlinearity (DNL) errors are reduced. In order to evaluate the idea, the proposed time-to-digital converter is designed in TSMC 45 nm CMOS technology and simulated. Comparison of the theoretical and simulation results confirms the benefits of the proposed TDC

A New Technique for the Design of Multi-Phase Voltage Controlled Oscillators

© 2017 World Scientific Publishing Company.In this work, a novel circuit structure for second-harmonic multi-phase voltage controlled oscillator (MVCO) is presented. The proposed MVCO is composed of (Formula presented.) ((Formula presented.) being an integer number and (Formula presented.)2) identical inductor–capacitor ((Formula presented.)) tank VCOs. In theory, this MVCO can provide 2(Formula presented.) different phase sinusoidal signals. A six-phase VCO based on the proposed structure is designed in a TSMC 0.18(Formula presented.)um CMOS process. Simulation results show that at the supply voltage of 0.8(Formula presented.)V, the total power consumption of the six-phase VCO circuit is about 1(Formula presented.)mW, the oscillation frequency is tunable from 2.3(Formula presented.)GHz to 2.5(Formula presented.)GHz when the control voltage varies from 0(Formula presented.)V to 0.8(Formula presented.)V, and the phase noise is lower than (Formula presented.)128(Formula presented.)dBc/Hz at 1(Formula presented.)MHz offset frequency. The proposed MVCO has lower phase noise, lower power consumption and more outputs than other related works in the literature.Peer reviewedFinal Accepted Versio

A 16 x 16 CMOS amperometric microelectrode array for simultaneous electrochemical measurements

There is a requirement for an electrochemical sensor technology capable of making multivariate measurements in environmental, healthcare, and manufacturing applications. Here, we present a new device that is highly parallelized with an excellent bandwidth. For the first time, electrochemical cross-talk for a chip-based sensor is defined and characterized. The new CMOS electrochemical sensor chip is capable of simultaneously taking multiple, independent electroanalytical measurements. The chip is structured as an electrochemical cell microarray, comprised of a microelectrode array connected to embedded self-contained potentiostats. Speed and sensitivity are essential in dynamic variable electrochemical systems. Owing to the parallel function of the system, rapid data collection is possible while maintaining an appropriately low-scan rate. By performing multiple, simultaneous cyclic voltammetry scans in each of the electrochemical cells on the chip surface, we are able to show (with a cell-to-cell pitch of 456 μm) that the signal cross-talk is only 12% between nearest neighbors in a ferrocene rich solution. The system opens up the possibility to use multiple independently controlled electrochemical sensors on a single chip for applications in DNA sensing, medical diagnostics, environmental sensing, the food industry, neuronal sensing, and drug discovery

Design of a single-chip pH sensor using a conventional 0.6-μm CMOS process

A pH sensor fabricated on a single chip by an unmodified, commercial 0.6-/spl μm CMOS process is presented. The sensor comprises a circuit for making differential measurements between an ion-sensitive field-effect transistor (ISFET) and a reference FET (REFET). The ISFET has a floating-gate structure and uses the silicon nitride passivation layer as a pH-sensitive insulator. As fabricated, it has a large threshold voltage that is postulated to be caused by a trapped charge on the floating gate. Ultraviolet radiation and bulk-substrate biasing is used to permanently modify the threshold voltage so that the ISFET can be used in a battery-operated circuit. A novel post-processing method using a single layer of photoresist is used to define the sensing areas and to provide robust encapsulation for the chip. The complete circuit, operating from a single 3-V supply, provides an output voltage proportional to pH and can be powered down when not required