A Fully Differential Digital CMOS Pulse UWB Generator

A new fully-digital CMOS pulse generator for impulse-radio Ultra-Wide-Band (UWB) systems is presented. First, the shape of the pulse which best fits the FCC regulation in the 3.1-5 GHz sub-band of the entire 3.1-10.6 GHz UWB bandwidth is derived and approximated using rectangular digital pulses. In particular, the number and width of pulses that approximate an ideal template is found through an ad-hoc optimization methodology. Then a fully differential digital CMOS circuit that synthesizes the pulse sequence is conceived and its functionality demonstrated through post-layout simulations. The results show a very good agreement with the FCC requirements and a low power consumptio

Differential temperature sensors: Review of applications in the test and characterization of circuits, usage and design methodology

Differential temperature sensors can be placed in integrated circuits to extract a signature ofthe power dissipated by the adjacent circuit blocks built in the same silicon die. This review paper firstdiscusses the singularity that differential temperature sensors provide with respect to other sensortopologies, with circuit monitoring being their main application. The paper focuses on the monitoringof radio-frequency analog circuits. The strategies to extract the power signature of the monitoredcircuit are reviewed, and a list of application examples in the domain of test and characterizationis provided. As a practical example, we elaborate the design methodology to conceive, step bystep, a differential temperature sensor to monitor the aging degradation in a class-A linear poweramplifier working in the 2.4 GHz Industrial Scientific Medical—ISM—band. It is discussed how,for this particular application, a sensor with a temperature resolution of 0.02 K and a high dynamicrange is required. A circuit solution for this objective is proposed, as well as recommendations for thedimensions and location of the devices that form the temperature sensor. The paper concludes with adescription of a simple procedure to monitor time variability.Postprint (published version

Hybrid MIMO Architectures for Millimeter Wave Communications: Phase Shifters or Switches?

Hybrid analog/digital MIMO architectures were recently proposed as an alternative for fully-digitalprecoding in millimeter wave (mmWave) wireless communication systems. This is motivated by the possible reduction in the number of RF chains and analog-to-digital converters. In these architectures, the analog processing network is usually based on variable phase shifters. In this paper, we propose hybrid architectures based on switching networks to reduce the complexity and the power consumption of the structures based on phase shifters. We define a power consumption model and use it to evaluate the energy efficiency of both structures. To estimate the complete MIMO channel, we propose an open loop compressive channel estimation technique which is independent of the hardware used in the analog processing stage. We analyze the performance of the new estimation algorithm for hybrid architectures based on phase shifters and switches. Using the estimated, we develop two algorithms for the design of the hybrid combiner based on switches and analyze the achieved spectral efficiency. Finally, we study the trade-offs between power consumption, hardware complexity, and spectral efficiency for hybrid architectures based on phase shifting networks and switching networks. Numerical results show that architectures based on switches obtain equal or better channel estimation performance to that obtained using phase shifters, while reducing hardware complexity and power consumption. For equal power consumption, all the hybrid architectures provide similar spectral efficiencies.Comment: Submitted to IEEE Acces

Towards a single-photon energy-sensitive pixel readout chip: pixel level ADCs and digital readout circuitry

Unlike conventional CMOS imaging, a single\ud photon imager detects each individual photon impinging on\ud a detector, accumulating the number of photons during a\ud certain time window and not the charge generated by the all\ud the photons hitting the detector during said time window.\ud The latest developments in the semiconductor industry\ud are allowing faster and more complex chips to be designed\ud and manufactured. With these developments in mind we are\ud working towards the next step in single photon X-ray imaging:\ud energy sensitive pixel readout chips. The goal is not only\ud to detect and count individual photons, but also to measure\ud the charge deposited in the detector by each photon, and\ud consequently determine its energy. Basically, we are aiming\ud at a spectrometer-in-a-pixel, or a “color X-ray camera”.\ud The approach we have followed towards this goal is the\ud design of small analog-to-digital-converters at the pixel level,\ud together with a very fast digital readout from the pixels to\ud the periphery of the chip, where the data will be transmitted\ud off-chip.\ud We will present here the design and measurement on prototype\ud chips of two different 4-bit pixel level ADCs. The\ud ADCs are optimized for very small area and low power, with\ud a resolution of 4-bits and a sample rate of 1 Msample/s. The\ud readout architecture is based around current-mode sense\ud amplifiers and asynchronous token-passing between the pixels.\ud This is done in order to achieve event-by-event readout\ud and, consequently, on-line imaging. We need to read eventby-\ud event (photon-by-photon), because we cannot have memory\ud on the pixels due to obvious size constraints. We use\ud current-mode sense amplifiers because they perform very\ud well in similar applications as very fast static-RAM readout

Analog Neural Programmable Optimizers in CMOS VLSI Technologies

A 3-μm CMOS IC is presented demonstrating the concept of an analog neural system for constrained optimization. A serial time-multiplexed general-purpose architecture is introduced for the real-time solution of this kind of problem in MOS VLSI. This architecture is a fully programmable and reconfigurable one exploiting SC techniques for the analog part and making extensive use of digital techniques for programmability

Silicon Pixel R&D for the CLIC Tracking Detector

The physics aims at the proposed high-energy $e^+e^-$ collider CLIC pose challenging demands on the performance of the detector system. Precise hit-time tagging, an excellent spatial resolutions, and a low mass are required for the vertex and tracking detectors. To meet these requirements, an all-silicon vertex and tracking detector system is foreseen, for which a broad R&D programme on a variety of novel silicon detector technologies is being pursued. For the ultra-low mass vertex detector, different hybrid technologies with innovative sensor concepts and interconnection techniques are explored. For the large-scale tracking detector, the focus of the R&D lies on monolithic HV-MAPS and HR-CMOS technologies. This contribution gives an overview of the ongoing activities with a focus on monolithic technologies for the CLIC tracking detector. Recent results from laboratory and test-beam measurement campaigns of the ATLASpix_Simple and the CLICTD sensor prototypes are presented.Comment: Proceedings for INSTR20, 10 pages, 9 figure