3 research outputs found
Design of a DCO based on Worst-Case Delay of a Self-Timed Counter and a Digitally controllable Delay Path
Delay path reconfiguration is used to control frequency output in Digitally Controlled Oscillators. In order to achieve a very low frequency range, if the delay path is not properly designed, this would result in large area overhead and leakage power loss. An alternative delay path is proposed for the DCO, based on a unit delay as the smallest possible delay, with added architecture to multiply the unit delay using digital control bits, this allows the delay output to be near-linear. The proposed delay path has two control modes, a 2-bits fine grain control and 6-bit coarse control. Simulation results show that the frequency of the DCO ranges from 34.92MHz to 448MHZ at 1.1V with maximum average power consumption of 358.27 mu W at 1.1V
Power-compute co-design for robust pervasive IoT applications
PhD ThesisThe modern development of internet of things (IoT) requires the IoT devices to be more
compact and energy autonomous. Many of them require to be able to operate with
unstable and low power supplies that come from various energy sources such as energy
harvesters. This creates a challenge for building IoT devices that need to be robust to
energy variations.
In this research we propose methods for improving energy characteristics of IoT
devices from the perspective of two main challenges: (i) improving the efficiency
and stability of power regulators, and (ii) enhancing the energy robustness of the IoT
devices. The existing design methods do not consider these two aspects holistically. One
important feature of our approach is holistic use of event-based, temporal representation
of data, which involves using asynchronous techniques and duty-cycle-based encoding.
For power regulation we use switched-capacitor converters (SCC) because they offer
compactness and ease of on-chip implementation. In this research we adapt the existing
methods and develop new techniques for SCC design based on asynchronous circuits.
This allows us to improve their performance and stability. We also investigate the
methods of parasitic charge redistribution, and apply them to self-oscillating SCC,
improving their performance. The key contribution within (i) is development of the
methods of SCC design with improved characteristics.
The majority of novel IoT systems are shifting towards the “AI at the edge” vision,
for example, involving neural networks (NN). We consider a perceptron-based neural
network as a typical IoT computing device. In our research we propose a novel
NN design approach using the principle of pulse-width modulation (PWM). PWMencoded
signals represent information with their duty cycle values which may be made
independent of the voltages and frequencies of the carrier signals. As a result, the device
is more robust to voltage variations, and, thus, the power regulation can be simplified.
This is the second major contribution addressing challenge (ii).
The advantages of the proposed methods are validated with simulations in the
Cadence environment. The simulations demonstrate the operation of the designed
power regulators, and the improvements of their efficiency. The simulations also
demonstrate the principle of operation of the PWM-based perceptron and prove its
power and frequency elasticity.
The thesis gives future research directions into a deeper study of the holistic co-design
of a variation-robust power-compute paradigm and its impact on developing future IoT
applications
Exploiting robustness in asynchronous circuits to design fine-tunable systems
PhD ThesisRobustness property in a circuit defines its tolerance to the effects of process, voltage and
temperature variations. The mode signaling and event communication between computing
units in a asynchronous circuits makes them inherently robust. The level of robustness
depends on the type of delay assumptions used in the design and specification process.
In this thesis, two approaches to exploiting robustness in asynchronous circuits to design
self-adapting and fine-tunable systems are investigated. In the first investigation, a Digitally
Controllable Oscillator (DCO) and a computing unit are integrated such that the operating
conditions of the computing unit modulated the operation of the DCO. In this investigation,
the computing unit which is a self-timed counter interacts with the DCO in a four-phase
handshake protocol. This mode of interaction ensures a DCO and computing unit system
that can fine-tune its operation to adapt to the effects of variations. In this investigation, it
is shown that such a system will operate correctly in wide range of voltage supply. In the
second investigation, a Digital Pulse-Width Modulator (DPWM) with coarse and fine-tune
controls is designed using two Kessels counters. The coarse control of the DPWM tuned the
pulse ratio and pulse frequency while the fine-tune control exploited the robustness property
of asynchronous circuits in an addition-based delay system to add or subtract delay(s) to
the pulse width while maintaining a constant pulse frequency. The DPWM realized gave
constant duty ratio regardless of the operating voltage. This type of DPWM has practical
application in a DC-DC converter circuit to tune the output voltage of the converter in high
resolution. The Kessels counter is a loadable self-timed modulo−n counter, which is realized
by decomposition using Horner’s method, specified and verified using formal asynchronous
design techniques. The decomposition method used introduced parallelism in the system by
dividing the counter into a systolic array of cells, with each cell further decomposed into
two parts that have distinct defined operations. Specification of the decomposed counter cell
parts operation was in three stages. The first stage employed high-level specification using
Labelled Petri nets (LPN). In this form, functional correctness of the decomposed counter is
modelled and verified. In the second stage, a cell part is specified by combing all possible
operations for that cell part in high-level form. With this approach, a combination of inputs
from a defined control block activated the correct operation for a cell part. In the final stage,
the LPNs were converted to Signal Transition Graphs, from which the logic circuits of the
cells were synthesized using the WorkCraft Tool. In this thesis, the Kessels counter was
implemented and fabricated in 350 nm CMOS Technology.Niger Delta Development Commission (NDD