44,102 research outputs found
Game-theoretic Resource Allocation Methods for Device-to-Device (D2D) Communication
Device-to-device (D2D) communication underlaying cellular networks allows
mobile devices such as smartphones and tablets to use the licensed spectrum
allocated to cellular services for direct peer-to-peer transmission. D2D
communication can use either one-hop transmission (i.e., in D2D direct
communication) or multi-hop cluster-based transmission (i.e., in D2D local area
networks). The D2D devices can compete or cooperate with each other to reuse
the radio resources in D2D networks. Therefore, resource allocation and access
for D2D communication can be treated as games. The theories behind these games
provide a variety of mathematical tools to effectively model and analyze the
individual or group behaviors of D2D users. In addition, game models can
provide distributed solutions to the resource allocation problems for D2D
communication. The aim of this article is to demonstrate the applications of
game-theoretic models to study the radio resource allocation issues in D2D
communication. The article also outlines several key open research directions.Comment: Accepted. IEEE Wireless Comms Mag. 201
Socially Trusted Collaborative Edge Computing in Ultra Dense Networks
Small cell base stations (SBSs) endowed with cloud-like computing
capabilities are considered as a key enabler of edge computing (EC), which
provides ultra-low latency and location-awareness for a variety of emerging
mobile applications and the Internet of Things. However, due to the limited
computation resources of an individual SBS, providing computation services of
high quality to its users faces significant challenges when it is overloaded
with an excessive amount of computation workload. In this paper, we propose
collaborative edge computing among SBSs by forming SBS coalitions to share
computation resources with each other, thereby accommodating more computation
workload in the edge system and reducing reliance on the remote cloud. A novel
SBS coalition formation algorithm is developed based on the coalitional game
theory to cope with various new challenges in small-cell-based edge systems,
including the co-provisioning of radio access and computing services,
cooperation incentives, and potential security risks. To address these
challenges, the proposed method (1) allows collaboration at both the user-SBS
association stage and the SBS peer offloading stage by exploiting the ultra
dense deployment of SBSs, (2) develops a payment-based incentive mechanism that
implements proportionally fair utility division to form stable SBS coalitions,
and (3) builds a social trust network for managing security risks among SBSs
due to collaboration. Systematic simulations in practical scenarios are carried
out to evaluate the efficacy and performance of the proposed method, which
shows that tremendous edge computing performance improvement can be achieved.Comment: arXiv admin note: text overlap with arXiv:1010.4501 by other author
A C++-embedded Domain-Specific Language for programming the MORA soft processor array
MORA is a novel platform for high-level FPGA programming of streaming vector and matrix operations, aimed at multimedia applications. It consists of soft array of pipelined low-complexity SIMD processors-in-memory (PIM). We present a Domain-Specific Language (DSL) for high-level programming of the MORA soft processor array. The DSL is embedded in C++, providing designers with a familiar language framework and the ability to compile designs using a standard compiler for functional testing before generating the FPGA bitstream using the MORA toolchain. The paper discusses the MORA-C++ DSL and the compilation route into the assembly for the MORA machine and provides examples to illustrate the programming model and performance
Instant restore after a media failure
Media failures usually leave database systems unavailable for several hours
until recovery is complete, especially in applications with large devices and
high transaction volume. Previous work introduced a technique called
single-pass restore, which increases restore bandwidth and thus substantially
decreases time to repair. Instant restore goes further as it permits read/write
access to any data on a device undergoing restore--even data not yet
restored--by restoring individual data segments on demand. Thus, the restore
process is guided primarily by the needs of applications, and the observed mean
time to repair is effectively reduced from several hours to a few seconds.
This paper presents an implementation and evaluation of instant restore. The
technique is incrementally implemented on a system starting with the
traditional ARIES design for logging and recovery. Experiments show that the
transaction latency perceived after a media failure can be cut down to less
than a second and that the overhead imposed by the technique on normal
processing is minimal. The net effect is that a few "nines" of availability are
added to the system using simple and low-overhead software techniques
Fully automated urban traffic system
The replacement of the driver with an automatic system which could perform the functions of guiding and routing a vehicle with a human's capability of responding to changing traffic demands was discussed. The problem was divided into four technological areas; guidance, routing, computing, and communications. It was determined that the latter three areas being developed independent of any need for fully automated urban traffic. A guidance system that would meet system requirements was not being developed but was technically feasible
A scalable multi-core architecture with heterogeneous memory structures for Dynamic Neuromorphic Asynchronous Processors (DYNAPs)
Neuromorphic computing systems comprise networks of neurons that use
asynchronous events for both computation and communication. This type of
representation offers several advantages in terms of bandwidth and power
consumption in neuromorphic electronic systems. However, managing the traffic
of asynchronous events in large scale systems is a daunting task, both in terms
of circuit complexity and memory requirements. Here we present a novel routing
methodology that employs both hierarchical and mesh routing strategies and
combines heterogeneous memory structures for minimizing both memory
requirements and latency, while maximizing programming flexibility to support a
wide range of event-based neural network architectures, through parameter
configuration. We validated the proposed scheme in a prototype multi-core
neuromorphic processor chip that employs hybrid analog/digital circuits for
emulating synapse and neuron dynamics together with asynchronous digital
circuits for managing the address-event traffic. We present a theoretical
analysis of the proposed connectivity scheme, describe the methods and circuits
used to implement such scheme, and characterize the prototype chip. Finally, we
demonstrate the use of the neuromorphic processor with a convolutional neural
network for the real-time classification of visual symbols being flashed to a
dynamic vision sensor (DVS) at high speed.Comment: 17 pages, 14 figure
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