43 research outputs found
Low Power Reversible Parallel Binary Adder/Subtractor
In recent years, Reversible Logic is becoming more and more prominent
technology having its applications in Low Power CMOS, Quantum Computing,
Nanotechnology, and Optical Computing. Reversibility plays an important role
when energy efficient computations are considered. In this paper, Reversible
eight-bit Parallel Binary Adder/Subtractor with Design I, Design II and Design
III are proposed. In all the three design approaches, the full Adder and
Subtractors are realized in a single unit as compared to only full Subtractor
in the existing design. The performance analysis is verified using number
reversible gates, Garbage input/outputs and Quantum Cost. It is observed that
Reversible eight-bit Parallel Binary Adder/Subtractor with Design III is
efficient compared to Design I, Design II and existing design.Comment: 12 pages,VLSICS Journa
A Synthesis Method for Quaternary Quantum Logic Circuits
Synthesis of quaternary quantum circuits involves basic quaternary gates and
logic operations in the quaternary quantum domain. In this paper, we propose
new projection operations and quaternary logic gates for synthesizing
quaternary logic functions. We also demonstrate the realization of the proposed
gates using basic quantum quaternary operations. We then employ our synthesis
method to design of quaternary adder and some benchmark circuits. Our results
in terms of circuit cost, are better than the existing works.Comment: 10 page
Ternary Logic Design in Topological Quantum Computing
A quantum computer can perform exponentially faster than its classical
counterpart. It works on the principle of superposition. But due to the
decoherence effect, the superposition of a quantum state gets destroyed by the
interaction with the environment. It is a real challenge to completely isolate
a quantum system to make it free of decoherence. This problem can be
circumvented by the use of topological quantum phases of matter. These phases
have quasiparticles excitations called anyons. The anyons are charge-flux
composites and show exotic fractional statistics. When the order of exchange
matters, then the anyons are called non-Abelian anyons. Majorana fermions in
topological superconductors and quasiparticles in some quantum Hall states are
non-Abelian anyons. Such topological phases of matter have a ground state
degeneracy. The fusion of two or more non-Abelian anyons can result in a
superposition of several anyons. The topological quantum gates are implemented
by braiding and fusion of the non-Abelian anyons. The fault-tolerance is
achieved through the topological degrees of freedom of anyons. Such degrees of
freedom are non-local, hence inaccessible to the local perturbations. In this
paper, the Hilbert space for a topological qubit is discussed. The Ising and
Fibonacci anyonic models for binary gates are briefly given. Ternary logic
gates are more compact than their binary counterparts and naturally arise in a
type of anyonic model called the metaplectic anyons. The mathematical model,
for the fusion and braiding matrices of metaplectic anyons, is the quantum
deformation of the recoupling theory. We proposed that the existing quantum
ternary arithmetic gates can be realized by braiding and topological charge
measurement of the metaplectic anyons
Low power reversible parallel binary adder/subtractor
In recent years, Reversible Logic is becoming more and more prominent technology having its applications in Low Power CMOS, Quantum Computing, Nanotechnology, and Optical Computing. Reversibility plays an important role when energy efficient computations are considered. In this paper, Reversible eight-bit Parallel Binary Adder/Subtractor with Design I, Design II and Design III are proposed. In all the three design approaches, the full Adder and Subtractors are realized in a single unit as compared to only full Subtractor in the existing design. The performance analysis is verified using number reversible gates, Garbage input/outputs and Quantum Cost. It is observed that Reversible eight-bit Parallel Binary Adder/Subtractor with Design III is efficient compared to Design I, Design II and existing design
Reversible Quantum-Dot Cellular Automata-Based Arithmetic Logic Unit
Quantum-dot cellular automata (QCA) are a promising nanoscale computing technology that exploits the quantum mechanical tunneling of electrons between quantum dots in a cell andelectrostatic interaction between dots in neighboring cells. QCA can achieve higher speed, lowerpower, and smaller areas than conventional, complementary metal-oxide semiconductor (CMOS)
technology. Developing QCA circuits in a logically and physically reversible manner can provide exceptional reductions in energy dissipation. The main challenge is to maintain reversibility down to the physical level. A crucial component of a computer’s central processing unit (CPU) is the arithmetic logic unit (ALU), which executes multiple logical and arithmetic functions on the data processed by the CPU. Current QCA ALU designs are either irreversible or logically reversible; however, they lack physical reversibility, a crucial requirement to increase energy efficiency. This paper shows a new multilayer design for a QCA ALU that can carry out 16 different operations and is both logically and physically reversible. The design is based on reversible majority gates, which are the key building blocks. We use QCA Designer-E software to simulate and evaluate energy dissipation.
The proposed logically and physically reversible QCA ALU offers an improvement of 88.8% in energy efficiency. Compared to the next most efficient 16-operation QCA ALU, this ALU uses 51% fewer QCA cells and 47% less area
Realization of Ternary Reversible Circuits Using Improved Gate Library
AbstractTernary logic has some distinct advantage over binary logic. In this paper we propose a synthesis approach for ternary reversible circuits using ternary reversible gates. Our method takes a boolean function as input. The input is provided as .pla file. The .pla file is first converted into ternary logic function, which can be represented as permutation. The gate library used for synthesis is Ternary Not, Ternary Toffoli and Ternary Toffoli+ (NT ,TT ,TT +). The proposed constructive method, generates 3-cycles from the permutation, and then each 3-cycle is mapped to (NT ,TT ,TT +) gate library. Experimental results show that the method generates lesser number of gates for some circuits compared to previously reported works