A sub-1-V Bandgap Voltage Reference in 32nm FinFET Technology

The bulk CMOS technology is expected to scale down to about 32nm node and likely the successor would be the FinFET. The FinFET is an ultra-thin body multi-gate MOS transistor with among other characteristics a much higher voltage gain compared to a conventional bulk MOS transistor [1]. Bandgap reference circuits cannot be directly ported from bulk CMOS technologies to SOI FinFET technologies, because both conventional diodes cannot be realized in thin SOI layers and also, area-efficient resistors are not readily available in processes with only metal(lic) gates. In this paper, a sub-1V bandgap reference circuit is implemented in a 32nm SOI FinFET technology, with an architecture that significantly reduces the required total resistance value

A fully integrated multiband frequency synthesizer for WLAN and WiMAX applications

This paper presents a fractional N frequency synthesizer which covers WLAN and WiMAX frequencies on a single chip. The synthesizer is fully integrated in 0.35μm BiCMOS AMS technology except crystal oscillator. The synthesizer operates at four frequency bands (3.101-3.352GHz, 3.379-3.727GHz, 3.7-4.2GHz, 4.5-5.321GHz) to provide the specifications of 802.16 and 802.11 a/b/g/y. A single on-chip LC - Gm based VCO is implemented as the core of this synthesizer. Different frequency bands are selected via capacitance switching and fine tuning is done using varactor for each of these bands. A bandgap reference circuit is implemented inside of this charge pump block to generate temperature and power supply independent reference currents. Simulated settling time is around 10μsec. Total power consumption is measured to be 118.6mW without pad driving output buffers from a 3.3V supply. The phase noise of the oscillator is lower than -116.4dbc/Hz for all bands. The circuit occupies 2.784 mm2 on Si substrate, including DC, Digital and RF pads

Design And Implementation Of Up-Conversion Mixer And Lc-Quadrature Oscillator For IEEE 802.11a WLAN Transmitter Application Utilizing 0.18 Pm CMOS Technology [TK7871.99.M44 H279 2008 f rb].

Perlumbaan implementasi litar terkamil radio, dengan kos yang rendah telah menggalakkan penggunaan teknologi CMOS. The drive for cost reduction has led to the use of CMOS technology for highly integrated radios

An accurate, trimless, high PSRR, low-voltage, CMOS bandgap reference IC

Bandgap reference circuits are used in a host of analog, digital, and mixed-signal systems to establish an accurate voltage standard for the entire IC. The accuracy of the bandgap reference voltage under steady-state (dc) and transient (ac) conditions is critical to obtain high system performance. In this work, the impact of process, power-supply, load, and temperature variations and package stresses on the dc and ac accuracy of bandgap reference circuits has been analyzed. Based on this analysis, the a bandgap reference that 1. has high dc accuracy despite process and temperature variations and package stresses, without resorting to expensive trimming or noisy switching schemes, 2. has high dc and ac accuracy despite power-supply variations, without using large off-chip capacitors that increase bill-of-material costs, 3. has high dc and ac accuracy despite load variations, without resorting to error-inducing buffers, 4. is capable of producing a sub-bandgap reference voltage with a low power-supply, to enable it to operate in modern, battery-operated portable applications, 5. utilizes a standard CMOS process, to lower manufacturing costs, and 6. is integrated, to consume less board space has been proposed. The functionality of critical components of the system has been verified through prototypes after which the performance of the complete system has been evaluated by integrating all the individual components on an IC. The proposed CMOS bandgap reference can withstand 5mA of load variations while generating a reference voltage of 890mV that is accurate with respect to temperature to the first order. It exhibits a trimless, dc 3-sigma accuracy performance of 0.84% over a temperature range of -40°C to 125°C and has a worst case ac power-supply ripple rejection (PSRR) performance of 30dB up to 50MHz using 60pF of on-chip capacitance. All the proposed techniques lead to the development of a CMOS bandgap reference that meets the low-cost, high-accuracy demands of state-of-the-art System-on-Chip environments.Ph.D.Committee Chair: Rincon-Mora, Gabriel; Committee Member: Ayazi, Farrokh; Committee Member: Bhatti, Pamela; Committee Member: Leach, W. Marshall; Committee Member: Morley, Thoma

A Flexible, Highly Integrated, Low Power pH Readout

Medical devices are widely employed in everyday life as wearable and implantable technologies make more and more technological breakthroughs. Implantable biosensors can be implanted into the human body for monitoring of relevant physiological parameters, such as pH value, glucose, lactate, CO2 [carbon dioxide], etc. For these applications the implantable unit needs a whole functional set of blocks such as micro- or nano-sensors, sensor signal processing and data generation units, wireless data transmitters etc., which require a well-designed implantable unit.Microelectronics technology with biosensors has caused more and more interest from both academic and industrial areas. With the advancement of microelectronics and microfabrication, it makes possible to fabricate a complete solution on an integrated chip with miniaturized size and low power consumption.This work presents a monolithic pH measurement system with power conditioning system for supply power derived from harvested energy. The proposed system includes a low-power, high linearity pH readout circuits with wide pH values (0-14) and a power conditioning unit based on low drop-out (LDO) voltage regulator. The readout circuit provides square-wave output with frequency being highly linear corresponding to the input pH values. To overcome the process variations, a simple calibration method is employed in the design which makes the output frequency stay constant over process, supply voltage and temperature variations. The prototype circuit is designed and fabricated in a standard 0.13-μm [micro-meter] CMOS process and shows good linearity to cover the entire pH value range from 0-14 while the voltage regulator provides a stable supply voltage for the system

A 1.2-V 10- µW NPN-Based Temperature Sensor in 65-nm CMOS With an Inaccuracy of 0.2 °C (3σ) From 70 °C to 125 °C

An NPN-based temperature sensor with digital output transistors has been realized in a 65-nm CMOS process. It achieves a batch-calibrated inaccuracy of ±0.5 ◦C (3¾) and a trimmed inaccuracy of ±0.2 ◦C (3¾) over the temperature range from −70 ◦C to 125 ◦C. This performance is obtained by the use of NPN transistors as sensing elements, the use of dynamic techniques, i.e. correlated double sampling and dynamic element matching, and a single room-temperature trim. The sensor draws 8.3 μA from a 1.2-V supply and occupies an area of 0.1 mm2

A low-power native NMOS-based bandgap reference operating from −55°C to 125°C with Li-Ion battery compatibility

Summary The paper describes the implementation of a bandgap reference based on native-MOSFET transistors for low-power sensor node applications. The circuit can operate from −55°C to 125°C and with a supply voltage ranging from 1.5 to 4.2 V. Therefore, it is compatible with the temperature range of automotive and military-aerospace applications, and for direct Li-Ion battery attach. Moreover, the circuit can operate without any dedicated start-up circuit, thanks to its inherent single operating point. A mathematical model of the reference circuit is presented, allowing simple portability across technology nodes, with current consumption and silicon area as design parameters. Implemented in a 55-nm CMOS technology, the voltage reference achieves a measured average (maximum) temperature coefficient of 28 ppm/°C (43 ppm/°C) and a measured sample-to-sample variation within 57 mV, with a current consumption of 420 nA at 27°C

Design, Modeling and Analysis of Non-classical Field Effect Transistors

Transistor scaling following per Moore\u27s Law slows down its pace when entering into nanometer regime where short channel effects (SCEs), including threshold voltage fluctuation, increased leakage current and mobility degradation, become pronounced in the traditional planar silicon MOSFET. In addition, as the demand of diversified functionalities rises, conventional silicon technologies cannot satisfy all non-digital applications requirements because of restrictions that stem from the fundamental material properties. Therefore, novel device materials and structures are desirable to fuel further evolution of semiconductor technologies. In this dissertation, I have proposed innovative device structures and addressed design considerations of those non-classical field effect transistors for digital, analog/RF and power applications with projected benefits. Considering device process difficulties and the dramatic fabrication cost, application-oriented device design and optimization are performed through device physics analysis and TCAD modeling methodology to develop design guidelines utilizing transistor\u27s improved characteristics toward application-specific circuit performance enhancement. Results support proposed device design methodologies that will allow development of novel transistors capable of overcoming limitation of planar nanoscale MOSFETs. In this work, both silicon and III-V compound devices are designed, optimized and characterized for digital and non-digital applications through calibrated 2-D and 3-D TCAD simulation. For digital functionalities, silicon and InGaAs MOSFETs have been investigated. Optimized 3-D silicon-on-insulator (SOI) and body-on-insulator (BOI) FinFETs are simulated to demonstrate their impact on the performance of volatile memory SRAM module with consideration of self-heating effects. Comprehensive simulation results suggest that the current drivability degradation due to increased device temperature is modest for both devices and corresponding digital circuits. However, SOI FinFET is recommended for the design of low voltage operation digital modules because of its faster AC response and better SCEs management than the BOI structure. The FinFET concept is also applied to the non-volatile memory cell at 22 nm technology node for low voltage operation with suppressed SCEs. In addition to the silicon technology, our TCAD estimation based on upper projections show that the InGaAs FinFET, with superior mobility and improved interface conditions, achieve tremendous drive current boost and aggressively suppressed SCEs and thereby a strong contender for low-power high-performance applications over the silicon counterpart. For non-digital functionalities, multi-fin FETs and GaN HEMT have been studied. Mixed-mode simulations along with developed optimization guidelines establish the realistic application potential of underlap design of silicon multi-Fin FETs for analog/RF operation. The device with underlap design shows compromised current drivability but improve analog intrinsic gain and high frequency performance. To investigate the potential of the novel N-polar GaN material, for the first time, I have provided calibrated TCAD modeling of E-mode N-polar GaN single-channel HEMT. In this work, I have also proposed a novel E-mode dual-channel hybrid MIS-HEMT showing greatly enhanced current carrying capability. The impact of GaN layer scaling has been investigated through extensive TCAD simulations and demonstrated techniques for device optimization

NEGATIVE BIAS TEMPERATURE INSTABILITY STUDIES FOR ANALOG SOC CIRCUITS

Negative Bias Temperature Instability (NBTI) is one of the recent reliability issues in sub threshold CMOS circuits. NBTI effect on analog circuits, which require matched device pairs and mismatches, will cause circuit failure. This work is to assess the NBTI effect considering the voltage and the temperature variations. It also provides a working knowledge of NBTI awareness to the circuit design community for reliable design of the SOC analog circuit. There have been numerous studies to date on the NBTI effect to analog circuits. However, other researchers did not study the implication of NBTI stress on analog circuits utilizing bandgap reference circuit. The reliability performance of all matched pair circuits, particularly the bandgap reference, is at the mercy of aging differential. Reliability simulation is mandatory to obtain realistic risk evaluation for circuit design reliability qualification. It is applicable to all circuit aging problems covering both analog and digital. Failure rate varies as a function of voltage and temperature. It is shown that PMOS is the reliabilitysusceptible device and NBTI is the most vital failure mechanism for analog circuit in sub-micrometer CMOS technology. This study provides a complete reliability simulation analysis of the on-die Thermal Sensor and the Digital Analog Converter (DAC) circuits and analyzes the effect of NBTI using reliability simulation tool. In order to check out the robustness of the NBTI-induced SOC circuit design, a bum-in experiment was conducted on the DAC circuits. The NBTI degradation observed in the reliability simulation analysis has given a clue that under a severe stress condition, a massive voltage threshold mismatch of beyond the 2mV limit was recorded. Bum-in experimental result on DAC proves the reliability sensitivity of NBTI to the DAC circuitry