Distributed Integrated Circuits: An Alternative Approach to High-Frequency Design

Distributed integrated circuits are presented as a methodology to design high-frequency communication building blocks. Distributed circuits operate based on multiple parallel signal paths working in synchronization that can be used to enhance the frequency of operation, combine power, and enhance the robustness of the design. These multiple signal paths usually result in strong couplings inside the circuit that necessitate a treatment spanning architecture, circuits, devices, and electromagnetic levels of abstraction

Open-ended evolution to discover analogue circuits for beyond conventional applications

This is the author's accepted manuscript. The final publication is available at Springer via http://dx.doi.org/10.1007/s10710-012-9163-8. Copyright @ Springer 2012.Analogue circuits synthesised by means of open-ended evolutionary algorithms often have unconventional designs. However, these circuits are typically highly compact, and the general nature of the evolutionary search methodology allows such designs to be used in many applications. Previous work on the evolutionary design of analogue circuits has focused on circuits that lie well within analogue application domain. In contrast, our paper considers the evolution of analogue circuits that are usually synthesised in digital logic. We have developed four computational circuits, two voltage distributor circuits and a time interval metre circuit. The approach, despite its simplicity, succeeds over the design tasks owing to the employment of substructure reuse and incremental evolution. Our findings expand the range of applications that are considered suitable for evolutionary electronics

Assembling strategies in extrinsic evolvable hardware with bi-directional incremental evolution

Bidirectional incremental evolution (BIE) has been proposed as a technique to overcome the ”stalling” effect in evolvable hardware applications. However preliminary results show perceptible dependence of performance of BIE and quality of evaluated circuit on assembling strategy applied during reverse stage of incremental evolution. The purpose of this paper is to develop assembling strategy that will assist BIE to produce relatively optimal solution with minimal computational effort (e.g. the minimal number of generations)

Generalized disjunction decomposition for evolvable hardware

Evolvable hardware (EHW) refers to self-reconfiguration hardware design, where the configuration is under the control of an evolutionary algorithm (EA). One of the main difficulties in using EHW to solve real-world problems is scalability, which limits the size of the circuit that may be evolved. This paper outlines a new type of decomposition strategy for EHW, the “generalized disjunction decomposition” (GDD), which allows the evolution of large circuits. The proposed method has been extensively tested, not only with multipliers and parity bit problems traditionally used in the EHW community, but also with logic circuits taken from the Microelectronics Center of North Carolina (MCNC) benchmark library and randomly generated circuits. In order to achieve statistically relevant results, each analyzed logic circuit has been evolved 100 times, and the average of these results is presented and compared with other EHW techniques. This approach is necessary because of the probabilistic nature of EA; the same logic circuit may not be solved in the same way if tested several times. The proposed method has been examined in an extrinsic EHW system using the$(1 + lambda)$evolution strategy. The results obtained demonstrate that GDD significantly improves the evolution of logic circuits in terms of the number of generations, reduces computational time as it is able to reduce the required time for a single iteration of the EA, and enables the evolution of larger circuits never before evolved. In addition to the proposed method, a short overview of EHW systems together with the most recent applications in electrical circuit design is provided

Synthesis of time-to-amplitude converter by mean coevolution with adaptive parameters

Copyright © 2011 the authors and Scientific Research Publishing Inc. This work is licensed under a Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/)The challenging task to synthesize automatically a time-to-amplitude converter, which unites by its functionality several digital circuits, has been successfully solved with the help of a novel methodology. The proposed approach is based on a paradigm according to which the substructures are regarded as additional mutation types and when ranged with other mutations form a new adaptive individual-level mutation technique. This mutation approach led to the discovery of an original coevolution strategy that is characterized by very low selection rates. Parallel island-model evolution has been running in a hybrid competitive-cooperative interaction throughout two incremental stages. The adaptive population size is applied for synchronization of the parallel evolutions

A probabilistic approach to analyse the evolutionary process in circuit design

One of the actual problems in the evolvable hardware is the evolvability of logic circuits. In order to understand better the nature of existing problem, the probabilistic analysis can be used. This paper aims to investigate how the circuit layout evolution is carried out. This is interesting thing to do for two main reasons. Firstly, to investigate what type of genes mostly influence on the algorithm performance in evolvable hardware. Secondly, to see how effective an allocation of active logic gates might be in a digital circuit design task. In order to achieve this goal we investigate the genotypes of the best chromosomes which bring some improvements in evolutionary process. The logic circuits have been evolved using circuit layout evolution

High-sensitivity large-area photodiode read-out using a divide-and-conquer technique

In this letter, we present a novel technique to increase the sensitivity of optical read-out with large integrated photodiodes (PD). It consists of manufacturing the PD in several pieces, instead of a single device, and connecting a dedicated transimpedance amplifier (TIA) to each of these pieces. The output signals of the TIAs are combined, achieving a higher signal-to-noise ratio than with the traditional approach. This work shows a remarkable improvement in the sensitivity and transimpedance without the need for additional modifications or compensation techniques. As a result, an increase in sensitivity of 7.9 dBm and transimpedance of 8.7 dBO for the same bandwidth is achieved when dividing the photodiode read-out into 16 parallel paths. The proposed divide-and-conquer technique can be applied to any TIA design, and it is also independent of the core amplifier structure and fabrication process, which means it is compatible with every technology allowing the integration of PDs

Radix-2 x 2 x 2 algorithm for the 3-D discrete hartley transform

The discrete Hartley transform (DHT) has proved to be a valuable tool in digital signal/image processing and communications and has also attracted research interests in many multidimensional applications. Although many fast algorithms have been developed for the calculation of one- and two-dimensional (1-D and 2-D) DHT, the development of multidimensional algorithms in three and more dimensions is still unexplored and has not been given similar attention; hence, the multidimensional Hartley transform is usually calculated through the row-column approach. However, proper multidimensional algorithms can be more efficient than the row-column method and need to be developed. Therefore, it is the aim of this paper to introduce the concept and derivation of the three-dimensional (3-D) radix-2 2X 2X algorithm for fast calculation of the 3-D discrete Hartley transform. The proposed algorithm is based on the principles of the divide-and-conquer approach applied directly in 3-D. It has a simple butterfly structure and has been found to offer significant savings in arithmetic operations compared with the row-column approach based on similar algorithms

Quantum Algorithms for Scientific Computing and Approximate Optimization

Quantum computation appears to offer significant advantages over classical computation and this has generated a tremendous interest in the field. In this thesis we study the application of quantum computers to computational problems in science and engineering, and to combinatorial optimization problems. We outline the results below. Algorithms for scientific computing require modules, i.e., building blocks, implementing elementary numerical functions that have well-controlled numerical error, are uniformly scalable and reversible, and that can be implemented efficiently. We derive quantum algorithms and circuits for computing square roots, logarithms, and arbitrary fractional powers, and derive worst-case error and cost bounds. We describe a modular approach to quantum algorithm design as a first step towards numerical standards and mathematical libraries for quantum scientific computing. A fundamental but computationally hard problem in physics is to solve the time-independent Schrödinger equation. This is accomplished by computing the eigenvalues of the corresponding Hamiltonian operator. The eigenvalues describe the different energy levels of a system. The cost of classical deterministic algorithms computing these eigenvalues grows exponentially with the number of system degrees of freedom. The number of degrees of freedom is typically proportional to the number of particles in a physical system. We show an efficient quantum algorithm for approximating a constant number of low-order eigenvalues of a Hamiltonian using a perturbation approach. We apply this algorithm to a special case of the Schrödinger equation and show that our algorithm succeeds with high probability, and has cost that scales polynomially with the number of degrees of freedom and the reciprocal of the desired accuracy. This improves and extends earlier results on quantum algorithms for estimating the ground state energy. We consider the simulation of quantum mechanical systems on a quantum computer. We show a novel divide and conquer approach for Hamiltonian simulation. Using the Hamiltonian structure, we can obtain faster simulation algorithms. Considering a sum of Hamiltonians we split them into groups, simulate each group separately, and combine the partial results. Simulation is customized to take advantage of the properties of each group, and hence yield refined bounds to the overall simulation cost. We illustrate our results using the electronic structure problem of quantum chemistry, where we obtain significantly improved cost estimates under mild assumptions. We turn to combinatorial optimization problems. An important open question is whether quantum computers provide advantages for the approximation of classically hard combinatorial problems. A promising recently proposed approach of Farhi et al. is the Quantum Approximate Optimization Algorithm (QAOA). We study the application of QAOA to the Maximum Cut problem, and derive analytic performance bounds for the lowest circuit-depth realization, for both general and special classes of graphs. Along the way, we develop a general procedure for analyzing the performance of QAOA for other problems, and show an example demonstrating the difficulty of obtaining similar results for greater depth. We show a generalization of QAOA and its application to wider classes of combinatorial optimization problems, in particular, problems with feasibility constraints. We introduce the Quantum Alternating Operator Ansatz, which utilizes more general unitary operators than the original QAOA proposal. Our framework facilitates low-resource implementations for many applications which may be particularly suitable for early quantum computers. We specify design criteria, and develop a set of results and tools for mapping diverse problems to explicit quantum circuits. We derive constructions for several important prototypical problems including Maximum Independent Set, Graph Coloring, and the Traveling Salesman problem, and show appealing resource cost estimates for their implementations