Vedic-Based Squarers with High Performance

Squaring operation represents a vital operation in various applications involving image processing, rectangular to polar coordinate conversion, and many other applications. For its importance, a novel design for a 6-bit squarer basing on the Vedic multiplier (VM) is offered in this work. The squarer design utilizes dedicated 3-bit squarer modules, a (3*3) VM, and an improved Brent-Kung Carry-Select Adder (IBK-CSLA) with the amended design of XOR gate to perform fast partial-products addition. The 6-bit squarer circuit can readily be expanded for larger sizes such as 12-bit and 24-bit numbers which are useful for squaring the mantissa part of  32-bit floating-point numbers. The paper also offers three architectures for 24- bit squarer using pipelining concept used in various stages. All these squaring circuits are designed in VHDL and implemented by Xilinx ISE13.2 and FPGA. The synthesis results reveal that the offered 6-bit, 12- bit, and 24- bit squarer circuits introduce eminent outcomes in terms of delay and area when utilizing IBK-CSLA with amended XOR gate. Also, it is found that the three architectures of 24- bit squarer present dissimilar delay and area, and the architecture design based on 3-bit squarer modules with  (3*3) VM introduces the lowest area and delay

Adaptive and hybrid schemes for efficient parallel squaring and cubing units

Squaring (X2) and cubing (X3) units are special operations of multiplication used in many applications, such as image compression, equalization, decoding and demodulation, 3D graphics, scientific computing, artificial neural networks, logarithmic number system, and multimedia application. They can also be an efficient way to compute other basic functions. Therefore, improving their performances is a goal for many researchers. This dissertation will discuss modification to algorithms to compute parallel squaring and cubing units in both signed and unsigned representation. After that, truncated technique is applied to improve their performance. Each unit is modeled and estimated to obtain its area, delay by using linear evaluation model. A C program was written to generate Hardware Description Language files for each unit. These units are simulated and verified in simulation. Moreover, area, delay, and power consumption are calculated for each unit and compared with those ones in previous approaches for both Virtex 5 Xilinx FPGA and IBM 65nm ASIC technologies

Implementation of ECC on FPGA using Scalable Architecture With equal Data and Key for WSN

Security of data transferred on the Wireless Sensor Network is of vital importance. In public key cryptography RSA algorithm has been used for a long time, but it does not meet the constraints of WSNs. Elliptic Curve Cryptography(ECC) has been employed recently because of its highest security for same length bit. ECC point multiplication operation is time consuming which affects the speed of encryption and decryption of data. Security in WSNs is addressed in our work, where a modified ECC is designed by performing the point multiplication using Montgomery multiplication technique that achieves considerable speed and with reduced area utilization. The ECC is first simulated on different FPGA devices, with key length 11, 112, 131 and 163 bits and the area-speed tradeoff is compared. ECC algorithm is implemented with software and hardware choosing Artix 7 XC7a100t-3csg324 FPGA which supports key lengths of 11, 112, 131 and 163 bits. When implemented on a Artix 7 FPGA, it completes 163 bit data encryption operation over GF(2163 ) in 1ms with the maximum frequency of 229MHz. The ECC algorithm is reconfigurable with low level to high level security with different bit key sizes. The proposed ECC algorithm modeled using VHDL and synthesized on Spartan 3 and 6, Virtex 4, 5 and 6 and Artix7 before the hardware implementation on Atrix 7. The design satisfies the needs of resource constrained devices by decreasing the encryption and decryption time to 1 ms with equal keylength and datasize, while device utilization is within 13%

THE PLAN-NET AS A GEOMETRY FOR ANALYSIS OF PRE-MODERN ARCHITECTURAL DESIGN AND LAYOUT

Thesis (Ph.D.) - Indiana University, Folklore and Ethnomusicology, 2013Limited Pre-Modern calculating skills favored geometry for design and layout. Technical limitations precluding durable, detailed measured drawings favored sequentially proportional steps transmitting information from design to construction. The Ancient Egyptian phrase "Casting the plan-net on the ground" implies a rectilinear network of geometrical lines serving to locate plan elements on the ground. Reconstruction of Polykleitos' Kanon demonstrates design parameters based on sequential proportionality that extracts a "correctly" proportioned human figure from an original square base figure. Fifteenth century booklets describe extraction of a completed architectural form from the base figure. Iconographic sources trace these Ancient World methods from their use in practical implementation to symbolization as eighteenth century remembrances in Free Mason paraphernalia. To associate floor plan elements with a rectilinear network, plan-net geometry manipulates proportional relationships of squares and rectangles in sequentially proportional steps. Geometrical design steps by divider and straightedge are identical to ground-lines steps by cord and peg, eliminating calculation from scale change. Marking plan features by plan-net analysis reveals an inherent geometrical unity that appears to cross diachronic and synchronic borders. Varied plan-net patterns offer a new perspective for classifying vernacular floor plans. Conformance to plan-net lines by indeterminate architectural elements validates elements in question and suggests other elements missing from the architectural or archeological record. Seeking to understand how a house is thought as Henry Glassie said, and if culture is pattern in the mind, then plan-net analysis renders such pattern visible, to be understood as a unity crossing boundaries of culture and time but whose products can be differentiated as artifacts localized within cultural and temporal boundaries. To understand what has disappeared from the record, we must be willing to imagine what was, and then test what is imagined to ascertain how it fits to what is