An intelligent approach to design three-dimensional aircraft sheet metal part model for manufacture

Aircraft sheet metal part manufacturing is a knowledge-intensive process, and the manufacturability and manufacturing information are required to be considered in three-dimensional (3D) model by knowledge reuse. This paper presents a 3D model structure of the aircraft sheet metal part and an intelligent approach to design the model for manufacture combining intelligent manufacturability analysis with manufacturing information definition. Processability of part, formability of material and cost of fabrication are proposed to analyse the manufacturability of the part. Knowledge base for manufacturability analysis is established, and knowledge is reused to evaluate the part’s manufacturability intelligently to meet the constraints of manufacturing conditions. Non-geometric information is defined in the 3D model to meet the needs of digital manufacturing and inspection using model-based technology. An example is given to describe the process of design for manufacture, which shows that the approach can realize the concurrent design and digital manufacturing of aircraft sheet metal

Neural modeling and space mapping: two approaches to circuit design

The drive in the microwave industry for manufacturability-driven design and time-to-market demands powerful and efficient computer-aided design tools. The need for statistical analysis and yield optimization coupled with the desire to use accurate physics-based and EM-based models leads to tasks that are computationally intensive using conventional approaches. We present two recent advances in the microwave CAD area, Artificial Neural Network (ANN) based modeling and Space Mapping (SM) based modeling for fast and accurate design of microwave components and circuits.Consejo Nacional de Ciencia y TecnologíaCarleton Universit

ATLAS IBL Pixel Upgrade

The upgrade for ATLAS detector will undergo different phase towards super-LHC. The first upgrade for the Pixel detector will consist of the construction of a new pixel layer which will be installed during the first shutdown of the LHC machine (LHC phase-I upgrade). The new detector, called Insertable B-Layer (IBL), will be inserted between the existing pixel detector and a new (smaller radius) beam-pipe at a radius of 3.3 cm. The IBL will require the development of several new technologies to cope with increase of radiation or pixel occupancy and also to improve the physics performance which will be achieved by reducing the pixel size and of the material budget. Three different promising sensor technologies (planar-Si, 3D-Si and diamond) are currently under investigation for the pixel detector. An overview of the project with particular emphasis on pixel module is presented in this paper.Comment: 3 pages, 3 figures, presented at the 12th Topical Seminar on Innovative Particle and Radiation Detectors (IPRD10) 7 - 10 June 2010, Siena (IT). Accepted by Nuclear Physics B (Proceedings Supplements) (2011

ATLAS IBL Pixel Upgrade

The upgrade for ATLAS detector will undergo different phase towards super-LHC. The first upgrade for the Pixel detector will consist of the construction of a new pixel layer which will be installed during the first shutdown of the LHC machine (LHC phase-I upgrade). The new detector, called Insertable B-Layer (IBL), will be inserted between the existing pixel detector and a new (smaller radius) beam-pipe at a radius of 3.3 cm. The IBL will require the development of several new technologies to cope with increase of radiation or pixel occupancy and also to improve the physics performance which will be achieved by reducing the pixel size and of the material budget. Three different promising sensor technologies (planar-Si, 3D-Si and diamond) are currently under investigation for the pixel detector. An overview of the project with particular emphasis on pixel module is presented in this paper.Comment: 3 pages, 3 figures, presented at the 12th Topical Seminar on Innovative Particle and Radiation Detectors (IPRD10) 7 - 10 June 2010, Siena (IT). Accepted by Nuclear Physics B (Proceedings Supplements) (2011

Ultra-Stretchable Interconnects for High-Density Stretchable Electronics

The exciting field of stretchable electronics (SE) promises numerous novel applications, particularly in-body and medical diagnostics devices. However, future advanced SE miniature devices will require high-density, extremely stretchable interconnects with micron-scale footprints, which calls for proven standardized (complementary metal-oxide semiconductor (CMOS)-type) process recipes using bulk integrated circuit (IC) microfabrication tools and fine-pitch photolithography patterning. Here, we address this combined challenge of microfabrication with extreme stretchability for high-density SE devices by introducing CMOS-enabled, free-standing, miniaturized interconnect structures that fully exploit their 3D kinematic freedom through an interplay of buckling, torsion, and bending to maximize stretchability. Integration with standard CMOS-type batch processing is assured by utilizing the Flex-to-Rigid (F2R) post-processing technology to make the back-end-of-line interconnect structures free-standing, thus enabling the routine microfabrication of highly-stretchable interconnects. The performance and reproducibility of these free-standing structures is promising: an elastic stretch beyond 2000% and ultimate (plastic) stretch beyond 3000%, with 10 million cycles at 1000% stretch with <1% resistance change. This generic technology provides a new route to exciting highly-stretchable miniature devices.Comment: 13 pages, 5 figure, journal publicatio

Course development in IC manufacturing

A traditional curriculum in electrical engineering separates semiconductor processing courses from courses in circuit design. As a result, manufacturing topics involving yield management and the study of random process variations impacting circuit behaviour are usually vaguely treated. The subject matter of this paper is to report a course developed at Texas A&amp;M University, USA, to compensate for the aforementioned shortcoming. This course attempts to link technological process and circuit design domains by emphasizing aspects such as process disturbance modeling, yield modeling, and defect-induced fault modeling. In a rapidly changing environment where high-end technologies are evolving towards submicron features and towards high transistor integration, these aspects are key factors to design for manufacturability. The paper presents the course's syllabus, a description of its main topics, and results on selected project assignments carried out during a normal academic semeste