Hardware prototyping and validation of a W-ΔDOR digital signal processor

Microwave tracking, usually performed by on ground processing of the signals coming from a spacecraft, represents a crucial aspect in every deep-space mission. Various noise sources, including receiver noise, affect these signals, limiting the accuracy of the radiometric measurements obtained from the radio link. There are several methods used for spacecraft tracking, including the Delta-Differential One-Way Ranging (ΔDOR) technique. In the past years, European Space Agency (ESA) missions relied on a narrowband ΔDOR system for navigation in the cruise phase. To limit the adverse effect of nonlinearities in the receiving chain, an innovative wideband approach to ΔDOR measurements has recently been proposed. This work presents the hardware implementation of a new version of the ESA X/Ka Deep Space Transponder based on the new tracking technique named Wideband ΔDOR (W-ΔDOR). The architecture of the new transponder guarantees backward compatibility with narrowband ΔDOR

Empirical Analysis of Chirp and Multitones Performances with a UWB Software Defined Radar: Range, Distance and Doppler

In this study, a protocol for an unbiased analysis of radar signals' performance. Using a novel UWB software-defined radar, range profile, Doppler profile and detection range are evaluated for both Linear Frequency Modulated pulse and Multitones. The radar was prototyped and is comparable in overall performance to software defined radar test-beds found in the literature. The measured performance was in agreement with the simulations

Hardware Implementation of Lossless Adaptive Compression of Data From a Hyperspectral Imager

Efficient onboard data compression can reduce the data volume from hyperspectral imagers on NASA and DoD spacecraft in order to return as much imagery as possible through constrained downlink channels. Lossless compression is important for signature extraction, object recognition, and feature classification capabilities. To provide onboard data compression, a hardware implementation of a lossless hyperspectral compression algorithm was developed using a field programmable gate array (FPGA). The underlying algorithm is the Fast Lossless (FL) compression algorithm reported in Fast Lossless Compression of Multispectral- Image Data (NPO-42517), NASA Tech Briefs, Vol. 30, No. 8 (August 2006), p. 26 with the modification reported in Lossless, Multi-Spectral Data Comressor for Improved Compression for Pushbroom-Type Instruments (NPO-45473), NASA Tech Briefs, Vol. 32, No. 7 (July 2008) p. 63, which provides improved compression performance for data from pushbroom-type imagers. An FPGA implementation of the unmodified FL algorithm was previously developed and reported in Fast and Adaptive Lossless Onboard Hyperspectral Data Compression System (NPO-46867), NASA Tech Briefs, Vol. 36, No. 5 (May 2012) p. 42. The essence of the FL algorithm is adaptive linear predictive compression using the sign algorithm for filter adaption. The FL compressor achieves a combination of low complexity and compression effectiveness that exceeds that of stateof- the-art techniques currently in use. The modification changes the predictor structure to tolerate differences in sensitivity of different detector elements, as occurs in pushbroom-type imagers, which are suitable for spacecraft use. The FPGA implementation offers a low-cost, flexible solution compared to traditional ASIC (application specific integrated circuit) and can be integrated as an intellectual property (IP) for part of, e.g., a design that manages the instrument interface. The FPGA implementation was benchmarked on the Xilinx Virtex IV LX25 device, and ported to a Xilinx prototype board. The current implementation has a critical path of 29.5 ns, which dictated a clock speed of 33 MHz. The critical path delay is end-to-end measurement between the uncompressed input data and the output compression data stream. The implementation compresses one sample every clock cycle, which results in a speed of 33 Msample/s. The implementation has a rather low device use of the Xilinx Virtex IV LX25, making the total power consumption of the implementation about 1.27 W

Design and Implementation of a Secondary Surveillance Radar/Identification Friend or Foe Transceiver Card

The performance of SSR/IFF equipment, i.e. the transponder or the interrogator, can be tested by means of an SSR/IFF test set, which is usually extremely expensive, hard to transport and requires end-user certificates. This dissertation thus focuses on the design and implementation of a short-range real- time SSR/IFF Transceiver Card (ITRC), which can be used as an experimental platform for SSR/IFF test applications. User requirements are provided and analysed, resulting in a system breakdown structure, where for each subsystem a summary of related concepts is presented in order to produce the technical requirements for the system. The hardware was designed to be smaller, lighter, less expensive and easy to repair than conventional SSR/IFF test sets. When it has been integrated with an existing SSR/IFF reply emulator, it is capable of generating and analysing RF SSR/IFF signals for modes 1, 2, 3/A, C and secure mode 4 at a frequency of 1030 MHz and 1090 MHz in order to test the functionality of the interrogator and transponder. Verification for the design was accomplished by testing the transceiver hardware and then integrating the system with SSR/IFF transponder and interrogator. The results achieved were found to be compliant with the user requirements

Secure ADS-B: Towards Airborne Communications Security in the Federal Aviation Administration\u27s Next Generation Air Transportation System

The U.S. Congress has mandated that all aircraft operating within the National Airspace System, military or civilian, be equipped with ADS-B transponders by the year 2020. The ADS-B aircraft tracking system, part of the Federal Aviation Administration\u27s NextGen overhaul of the Air Transportation System, replaces Radar-based surveillance with a more accurate satellite-based surveillance system. However, the unencrypted nature of ADS-B communication poses an operational security risk to military and law enforcement aircraft conducting sensitive missions. The non-standard format of its message and the legacy communication channels used by its transponders make the ADS-B system unsuitable for traditional encryption mechanisms. FPE, a recent development in cryptography, provides the ability to encrypt arbitrarily formatted data without padding or truncation. Indeed, three new algorithms recommended by the NIST, may be suitable for encryption of ADS-B messages. This research assesses the security and hardware performance characteristics of the FF1, FF2, and FF3 algorithms, in terms of entropy of ciphertext, operational latency and resource utilization when implemented on a Field-Programmable Gate Array. While all of the algorithms inherit the security characteristics of the underlying AES block cipher, they exhibit differences in their performance profiles. Findings demonstrate that a Bump-in-the-Wire FPE cryptographic engine is a suitable solution for retrofitting encryption to ADS-B communication

Optical network democratization

The current Internet infrastructure is not able to support independent evolution and innovation at physical and network layer functionalities, protocols and services, while at same time supporting the increasing bandwidth demands of evolving and heterogeneous applications. This paper addresses this problem by proposing a completely democratized optical network infrastructure. It introduces the novel concepts of the optical white box and bare metal optical switch as key technology enablers for democratizing optical networks. These are programmable optical switches whose hardware is loosely connected internally and is completely separated from their control software. To alleviate their complexity, a multi-dimensional abstraction mechanism using software-defined network technology is proposed. It creates a universal model of the proposed switches without exposing their technological details. It also enables a conventional network programmer to develop network applications for control of the optical network without specific technical knowledge of the physical layer. Furthermore, a novel optical network virtualization mechanism is proposed, enabling the composition and operation of multiple coexisting and application-specific virtual optical networks sharing the same physical infrastructure. Finally, the optical white box and the abstraction mechanism are experimentally evaluated, while the virtualization mechanism is evaluated with simulation.</jats:p

SecuCode: Intrinsic PUF Entangled Secure Wireless Code Dissemination for Computational RFID Devices

The simplicity of deployment and perpetual operation of energy harvesting devices provides a compelling proposition for a new class of edge devices for the Internet of Things. In particular, Computational Radio Frequency Identification (CRFID) devices are an emerging class of battery-free, computational, sensing enhanced devices that harvest all of their energy for operation. Despite wireless connectivity and powering, secure wireless firmware updates remains an open challenge for CRFID devices due to: intermittent powering, limited computational capabilities, and the absence of a supervisory operating system. We present, for the first time, a secure wireless code dissemination (SecuCode) mechanism for CRFIDs by entangling a device intrinsic hardware security primitive Static Random Access Memory Physical Unclonable Function (SRAM PUF) to a firmware update protocol. The design of SecuCode: i) overcomes the resource-constrained and intermittently powered nature of the CRFID devices; ii) is fully compatible with existing communication protocols employed by CRFID devices in particular, ISO-18000-6C protocol; and ii) is built upon a standard and industry compliant firmware compilation and update method realized by extending a recent framework for firmware updates provided by Texas Instruments. We build an end-to-end SecuCode implementation and conduct extensive experiments to demonstrate standards compliance, evaluate performance and security.Comment: Accepted to the IEEE Transactions on Dependable and Secure Computin