7,556 research outputs found
A new look at the conditions for the synthesis of speed-independent circuits
This paper presents a set of sufficient conditions for the gate-level synthesis of speed-independent circuits when constrained to a given class of gate library. Existing synthesis methodologies are restricted to architectures that use simple AND-gates, and do not exploit the advantages offered by the existence of complex gates. The use of complex gates increases the speed and reduces the area of the circuits. These improvements are achieved because of (1) the elimination of the distributivity, signal persistency and unique minimal state requirements imposed by other techniques; (2) the reduction in the number of internal signals necessary to guarantee the synthesis; and finally (3) the utilization of optimization techniques to reduce the fan-in of the involved gates and the number of required memory elements.Peer ReviewedPostprint (published version
A temporal logic approach to modular design of synthetic biological circuits
We present a new approach for the design of a synthetic biological circuit
whose behaviour is specified in terms of signal temporal logic (STL) formulae.
We first show how to characterise with STL formulae the input/output behaviour
of biological modules miming the classical logical gates (AND, NOT, OR). Hence,
we provide the regions of the parameter space for which these specifications
are satisfied. Given a STL specification of the target circuit to be designed
and the networks of its constituent components, we propose a methodology to
constrain the behaviour of each module, then identifying the subset of the
parameter space in which those constraints are satisfied, providing also a
measure of the robustness for the target circuit design. This approach, which
leverages recent results on the quantitative semantics of Signal Temporal
Logic, is illustrated by synthesising a biological implementation of an
half-adder
Latency Optimized Asynchronous Early Output Ripple Carry Adder based on Delay-Insensitive Dual-Rail Data Encoding
Asynchronous circuits employing delay-insensitive codes for data
representation i.e. encoding and following a 4-phase return-to-zero protocol
for handshaking are generally robust. Depending upon whether a single
delay-insensitive code or multiple delay-insensitive code(s) are used for data
encoding, the encoding scheme is called homogeneous or heterogeneous
delay-insensitive data encoding. This article proposes a new latency optimized
early output asynchronous ripple carry adder (RCA) that utilizes single-bit
asynchronous full adders (SAFAs) and dual-bit asynchronous full adders (DAFAs)
which incorporate redundant logic and are based on the delay-insensitive
dual-rail code i.e. homogeneous data encoding, and follow a 4-phase
return-to-zero handshaking. Amongst various RCA, carry lookahead adder (CLA),
and carry select adder (CSLA) designs, which are based on homogeneous or
heterogeneous delay-insensitive data encodings which correspond to the
weak-indication or the early output timing model, the proposed early output
asynchronous RCA that incorporates SAFAs and DAFAs with redundant logic is
found to result in reduced latency for a dual-operand addition operation. In
particular, for a 32-bit asynchronous RCA, utilizing 15 stages of DAFAs and 2
stages of SAFAs leads to reduced latency. The theoretical worst-case latencies
of the different asynchronous adders were calculated by taking into account the
typical gate delays of a 32/28nm CMOS digital cell library, and a comparison is
made with their practical worst-case latencies estimated. The theoretical and
practical worst-case latencies show a close correlation....Comment: arXiv admin note: text overlap with arXiv:1704.0761
A 16 channel high-voltage driver with 14 bit resolution for driving piezoelectric actuators
A high-voltage, 16 channel driver with a maximum voltage of 72 volt and 14 bit resolution in a high-voltage CMOS (HV-CMOS) process is presented. This design incorporates a 14 bit monotonic by design DAC together with a high-voltage complementary class AB output stage for each channel. All 16 channels are used for driving a piezoelectric actuator within the control loop of a micropositioning system. Since the output voltages are static most of the time, a class AB amplifier is used, implementing voltage feedback to achieve 14 bit accuracy. The output driver consists of a push-pull stage with a built-in output current limitation and high-impedance mode. Also a protection circuit is added which limits the internal current when the output voltage saturates against the high-voltage rail. The 14 bit resolution of each channel is generated with a segmented resistor string DAC which assures monotonic by design behavior by using leapfrogging of the buffers used between segments. A diagonal shuffle layout is used for the resistor strings leading to cancellation of first order process gradients. The dense integration of 16 channels with high peak currents results in crosstalk, countered in this design by using staggered switching and resampling of the output voltages
A Multi-objective Perspective for Operator Scheduling using Fine-grained DVS Architecture
The stringent power budget of fine grained power managed digital integrated
circuits have driven chip designers to optimize power at the cost of area and
delay, which were the traditional cost criteria for circuit optimization. The
emerging scenario motivates us to revisit the classical operator scheduling
problem under the availability of DVFS enabled functional units that can
trade-off cycles with power. We study the design space defined due to this
trade-off and present a branch-and-bound(B/B) algorithm to explore this state
space and report the pareto-optimal front with respect to area and power. The
scheduling also aims at maximum resource sharing and is able to attain
sufficient area and power gains for complex benchmarks when timing constraints
are relaxed by sufficient amount. Experimental results show that the algorithm
that operates without any user constraint(area/power) is able to solve the
problem for most available benchmarks, and the use of power budget or area
budget constraints leads to significant performance gain.Comment: 18 pages, 6 figures, International journal of VLSI design &
Communication Systems (VLSICS
Iterative greedy algorithm for solving the FIR paraunitary approximation problem
In this paper, a method for approximating a multi-input multi-output (MIMO) transfer function by a causal finite-impulse response (FIR) paraunitary (PU) system in a weighted least-squares sense is presented. Using a complete parameterization of FIR PU systems in terms of Householder-like building blocks, an iterative algorithm is proposed that is greedy in the sense that the observed mean-squared error at each iteration is guaranteed to not increase. For certain design problems in which there is a phase-type ambiguity in the desired response, which is formally defined in the paper, a phase feedback modification is proposed in which the phase of the FIR approximant is fed back to the desired response. With this modification in effect, it is shown that the resulting iterative algorithm not only still remains greedy, but also offers a better magnitude-type fit to the desired response. Simulation results show the usefulness and versatility of the proposed algorithm with respect to the design of principal component filter bank (PCFB)-like filter banks and the FIR PU interpolation problem. Concerning the PCFB design problem, it is shown that as the McMillan degree of the FIR PU approximant increases, the resulting filter bank behaves more and more like the infinite-order PCFB, consistent with intuition. In particular, this PCFB-like behavior is shown in terms of filter response shape, multiresolution, coding gain, noise reduction with zeroth-order Wiener filtering in the subbands, and power minimization for discrete multitone (DMT)-type transmultiplexers
Unconstrained evolution of close-to-ideal "LCR" low-pass filter
The unconstrained evolution has already been applied in the past towards design of digital circuits, and extraordinary results have been obtained, including generation of more compact circuits with smaller number of electronic components. In this paper the unconstrained evolution method is developed for analogue circuits. At first, the method is probed on the design of analogue low-pass filter with standard transition band. The algorithm produced the best results in terms of quality of the circuits evolved and evolutionary resources required. Then, the new methodology is applied towards more sophisticated task, the close-to-ideal low-pass filter. The new methodology developed differs from previous ones by its simplicity and represents one of the first attempts to apply evolutionary strategy towards the analogue circuit design. The obtained results are compared in details with low-pass filters previously designed
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