Design and implementation of the AMCC self-timed microprocessor in FPGAs

Multiple myeloma (MM) is characterized by abnormal proliferation of clonal plasma cells or monoclonal plasmacytosis, resulting in accumulation of clonal immunoglobulins. Monoclonal gammopathy of unknown significance (MGUS) is considered a premorbid stage for developing MM. Studies have shown an increased risk of MGUS in first-degree relatives of patients with MM. Detection of immunoglobulin heavy chain gene (IGH) rearrangement provides a useful tool for assessing clonality. The aim of this study was to determine clonality in peripheral blood samples from 61 healthy first-degree relatives of MM probands by sorting circulating lymphocytes and detection of the IGH rearrangements in these cells. We detected 16 out of 61 (26.2 %) relatives with monoclonal complete and incomplete IGH rearrangements; only three of them showed elevated monoclonal immunoglobulin in the serum protein electrophoresis. We conclude that this strategy is able to identify efficiently clonality in peripheral blood samples from first-degree relatives of patients with MM, who have a non-negligible risk of developing MGUS or other plasma cell dyscrasias. " 2014 Springer Science+Business Media New York.",,,,,,"10.1007/s12032-014-0900-0",,,"http://hdl.handle.net/20.500.12104/40570","http://www.scopus.com/inward/record.url?eid=2-s2.0-84894419489&partnerID=40&md5=ca4f4724ed19b5eed49dc88e6fd9862b",,,,,,"4",,"Medical Oncology",,,,"31",,"Scopu

Design and Implementation of the AMCC Self-Timed Microprocessor in FPGAs

The development of processors with full custom technology has some disadvantages, such as the time used to design the processors and the cost of the implementation. In this article we used the programmable circuits FPGA such as an option of low cost for the development and implementation of Self-Timed (ST) systems. In addition it describes the architecture and the modules that compose the Asynchronous Microprocessor of Centralized Control (AMCC), and reviews the results of the occupation in the implementation of the FPGA. The operation of this processor only requires of an external pulse to the input of the first asynchronous control block, and with this pulse the sequence of request-recognition of the control unit begins, that it activates the cycle search and it begins the process of execution of the instructions, without the need of having a clock feeding the system. Once concluded the program, the microprocessor stops and include inherently the stoppable clock feature; i.e., circuit is stopped if it is not required (minimal dynamic consumption). Until it is activated again by an external request signal