REAL-TIME ADAPTIVE PULSE COMPRESSION ON RECONFIGURABLE, SYSTEM-ON-CHIP (SOC) PLATFORMS

New radar applications need to perform complex algorithms and process a large quantity of data to generate useful information for the users. This situation has motivated the search for better processing solutions that include low-power high-performance processors, efficient algorithms, and high-speed interfaces. In this work, hardware implementation of adaptive pulse compression algorithms for real-time transceiver optimization is presented, and is based on a System-on-Chip architecture for reconfigurable hardware devices. This study also evaluates the performance of dedicated coprocessors as hardware accelerator units to speed up and improve the computation of computing-intensive tasks such matrix multiplication and matrix inversion, which are essential units to solve the covariance matrix. The tradeoffs between latency and hardware utilization are also presented. Moreover, the system architecture takes advantage of the embedded processor, which is interconnected with the logic resources through high-performance buses, to perform floating-point operations, control the processing blocks, and communicate with an external PC through a customized software interface. The overall system functionality is demonstrated and tested for real-time operations using a Ku-band testbed together with a low-cost channel emulator for different types of waveforms

An FPGA/MPSoC Based Low Latency Onboard SAR Processor

This paper describes the concept and prototype implementation of a low latency spaceborne onboard Synthetic Aperture Radar (SAR) processor runing on a Multi-Processor-System-On-Chip (MPSoC) computing device combining an ARM processor and a Field-Programmable-Gate-Array (FPGA). The SAR processor is designed to generate SAR imagery from TerraSAR-X stripmap data for subsequent ship detection and sea state determination. Low latency data processing is a key development goal. Currently, a raw data block of 8k×32k samples, covering 375 km^2 to 500 km^2 , is focused on the hardware within 4 s. Together with an attached level-2 ship detection, wind, and sea state processor, running on the same device, a SAR data processing chain for generation of maritime alerts is formed. This chain is part of a larger prototype system being developed in the frame of the H2020 EO-ALERT project which further comprises an optical data chain, data compression/encryption, and scheduling on multiple reconfigurable MPSoC boards

Signal processing architectures for automotive high-resolution MIMO radar systems

To date, the digital signal processing for an automotive radar sensor has been handled in an efficient way by general purpose signal processors and microcontrollers. However, increasing resolution requirements for automated driving on the one hand, as well as rapidly growing numbers of manufactured sensors on the other hand, can provoke a paradigm change in the near future. The design and development of highly specialized hardware accelerators could become a viable option - at least for the most demanding processing steps with data rates of several gigabits per second. In this work, application-specific signal processing architectures for future high-resolution multiple-input and multiple-output (MIMO) radar sensors are designed, implemented, investigated and optimized. A focus is set on real-time performance such that even sophisticated algorithms can be computed sufficiently fast. The full processing chain from the received baseband signals to a list of detections is considered, comprising three major steps: Spectrum analysis, target detection and direction of arrival estimation. The developed architectures are further implemented on a field-programmable gate array (FPGA) and important measurements like resource consumption, power dissipation or data throughput are evaluated and compared with other examples from literature. A substantial dataset, based on more than 3600 different parametrizations and variants, has been established with the help of a model-based design space exploration and is provided as part of this work. Finally, an experimental radar sensor has been built and is used under real-world conditions to verify the effectiveness of the proposed signal processing architectures.Bisher wurde die digitale Signalverarbeitung für automobile Radarsensoren auf eine effiziente Art und Weise von universell verwendbaren Mikroprozessoren bewältigt. Jedoch können steigende Anforderungen an das Auflösungsvermögen für hochautomatisiertes Fahren einerseits, sowie schnell wachsende Stückzahlen produzierter Sensoren andererseits, einen Paradigmenwechsel in naher Zukunft bewirken. Die Entwicklung von hochgradig spezialisierten Hardwarebeschleunigern könnte sich als eine praktikable Alternative etablieren - zumindest für die anspruchsvollsten Rechenschritte mit Datenraten von mehreren Gigabits pro Sekunde. In dieser Arbeit werden anwendungsspezifische Signalverarbeitungsarchitekturen für zukünftige, hochauflösende, MIMO Radarsensoren entworfen, realisiert, untersucht und optimiert. Der Fokus liegt dabei stets auf der Echtzeitfähigkeit, sodass selbst anspruchsvolle Algorithmen in einer ausreichend kurzen Zeit berechnet werden können. Die komplette Signalverarbeitungskette, beginnend von den empfangenen Signalen im Basisband bis hin zu einer Liste von Detektion, wird in dieser Arbeit behandelt. Die Kette gliedert sich im Wesentlichen in drei größere Teilschritte: Spektralanalyse, Zieldetektion und Winkelschätzung. Des Weiteren werden die entwickelten Architekturen auf einem FPGA implementiert und wichtige Kennzahlen wie Ressourcenverbrauch, Stromverbrauch oder Datendurchsatz ausgewertet und mit anderen Beispielen aus der Literatur verglichen. Ein umfangreicher Datensatz, welcher mehr als 3600 verschiedene Parametrisierungen und Varianten beinhaltet, wurde mit Hilfe einer modellbasierten Entwurfsraumexploration erstellt und ist in dieser Arbeit enthalten. Schließlich wurde ein experimenteller Radarsensor aufgebaut und dazu benutzt, die entworfenen Signalverarbeitungsarchitekturen unter realen Umgebungsbedingungen zu verifizieren

A Ground-based L-band Radar System for Monitoring Forest Temporal Dynamics

L-band FMCW radar is implemented for monitoring forest dynamics. It took short-term and long-term measurements with an internal calibration system that guarantees stability and precision. The radar data is compared to in-situ measurement, which infers causal relationships between radar backscatter signal and forest physiology index such as tree dielectric. This paper explains the relationship between radar signals and environmental components such as precipitation based on the measurement. The radar demonstrates some interesting observations, for example, trees\u27 daily activity and freeze-thaw process

A review of synthetic-aperture radar image formation algorithms and implementations: a computational perspective

Designing synthetic-aperture radar image formation systems can be challenging due to the numerous options of algorithms and devices that can be used. There are many SAR image formation algorithms, such as backprojection, matched-filter, polar format, Range–Doppler and chirp scaling algorithms. Each algorithm presents its own advantages and disadvantages considering efficiency and image quality; thus, we aim to introduce some of the most common SAR image formation algorithms and compare them based on these two aspects. Depending on the requisites of each individual system and implementation, there are many device options to choose from, for in stance, FPGAs, GPUs, CPUs, many-core CPUs, and microcontrollers. We present a review of the state of the art of SAR imaging systems implementations. We also compare such implementations in terms of power consumption, execution time, and image quality for the different algorithms used.info:eu-repo/semantics/publishedVersio

Time domain based image generation for synthetic aperture radar on field programmable gate arrays

Aerial images are important in different scenarios including surface cartography, surveillance, disaster control, height map generation, etc. Synthetic Aperture Radar (SAR) is one way to generate these images even through clouds and in the absence of daylight. For a wide and easy usage of this technology, SAR systems should be small, mounted to Unmanned Aerial Vehicles (UAVs) and process images in real-time. Since UAVs are small and lightweight, more robust (but also more complex) time-domain algorithms are required for good image quality in case of heavy turbulence. Typically the SAR data set size does not allow for ground transmission and processing, while the UAV size does not allow for huge systems and high power consumption to process the data. A small and energy-efficient signal processing system is therefore required. To fill the gap between existing systems that are capable of either high-speed processing or low power consumption, the focus of this thesis is the analysis, design, and implementation of such a system. A survey shows that most architectures either have to high power budgets or too few processing capabilities to match real-time requirements for time-domain-based processing. Therefore, a Field Programmable Gate Array (FPGA) based system is designed, as it allows for high performance and low-power consumption. The Global Backprojection (GBP) is implemented, as it is the standard time-domain-based algorithm which allows for highest image quality at arbitrary trajectories at the complexity of O(N3). To satisfy real-time requirements under all circumstances, the accelerated Fast Factorized Backprojection (FFBP) algorithm with a complexity of O(N2logN) is implemented as well, to allow for a trade-off between image quality and processing time. Additionally, algorithm and design are enhanced to correct the failing assumptions for Frequency Modulated Continuous Wave (FMCW) Radio Detection And Ranging (Radar) data at high velocities. Such sensors offer high-resolution data at considerably low transmit power which is especially interesting for UAVs. A full analysis of all algorithms is carried out, to design a highly utilized architecture for maximum throughput. The process covers the analysis of mathematical steps and approximations for hardware speedup, the analysis of code dependencies for instruction parallelism and the analysis of streaming capabilities, including memory access and caching strategies, as well as parallelization considerations and pipeline analysis. Each architecture is described in all details with its surrounding control structure. As proof of concepts, the architectures are mapped on a Virtex 6 FPGA and results on resource utilization, runtime and image quality are presented and discussed. A special framework allows to scale and port the design to other FPGAs easily and to enable for maximum resource utilization and speedup. The result is streaming architectures that are capable of massive parallelization with a minimum in system stalls. It is shown that real-time processing on FPGAs with strict power budgets in time-domain is possible with the GBP (mid-sized images) and the FFBP (any image size with a trade-off in quality), allowing for a UAV scenario

The detection of unknown waveforms in ESM receivers: FFT-based real-time solutions

Radars and airborne electronic support measures (ESMs) systems are locked in a tactical battle to detect each other whilst remaining undetected. Traditionally, the ESM system has a range advantage. Low probability of intercept (LPI) waveform designers are, however, more heavily exploiting the matched filter radar advantage and hence degrading the range advantage. There have been literature and internal, SELEX Galileo proposals to regain some ESM processing gain of low probability of intercept (LPI) waveforms. This study, however, has sought digital signal processing (DSP) solutions which are: (1) computationally simple; (2) backward-compatible with existing SELEX Galileo digital receivers (DRxs) and (3) have low resource requirements. The two contributions are complementary and result in a detector which is suitable for detection of most radar waveforms. The first contribution is the application of spatially variant apodization (SVA) in a detection role. Compared to conventional window functions, SVA was found to be beneficial for the detection of sinusoidal radar waveforms as it surpassed the fixed window function detectors in all scenarios tested. The second contribution shows by simulation that simple spectral smoothing techniques improved DRx LPI detection capability to a level similar to more complicated non-parametric spectral estimators and far in excess of the conventional (modified) periodogram. The DSP algorithms were implemented using model-based design (MBD). The implication is that a detector with improved conventional and LPI waveform detection capability can be created from the intellectual property (IP). Estimates of the improvement in SELEX Galileo DRx system detection range are provided in the conclusion

Direct digital synthesizers : theory, design and applications

Traditional designs of high bandwidth frequency synthesizers employ the use of a phase-locked-loop (PLL). A direct digital synthesizer (DDS) provides many significant advantages over the PLL approaches. Fast settling time, sub-Hertz frequency resolution, continuous-phase switching response and low phase noise are features easily obtainable in the DDS systems. Although the principle of the DDS has been known for many years, the DDS did not play a dominant role in wideband frequency generation until recent years. Earlier DDSs were limited to produce narrow bands of closely spaced frequencies, due to limitations of digital logic and D/A-converter technologies. Recent advantages in integrated circuit (IC) technologies have brought about remarkable progress in this area. By programming the DDS, adaptive channel bandwidths, modulation formats, frequency hopping and data rates are easily achieved. This is an important step towards a "software-radio" which can be used in various systems. The DDS could be applied in the modulator or demodulator in the communication systems. The applications of DDS are restricted to the modulator in the base station. The aim of this research was to find an optimal front-end for a transmitter by focusing on the circuit implementations of the DDS, but the research also includes the interface to baseband circuitry and system level design aspects of digital communication systems. The theoretical analysis gives an overview of the functioning of DDS, especially with respect to noise and spurs. Different spur reduction techniques are studied in detail. Four ICs, which were the circuit implementations of the DDS, were designed. One programmable logic device implementation of the CORDIC based quadrature amplitude modulation (QAM) modulator was designed with a separate D/A converter IC. For the realization of these designs some new building blocks, e.g. a new tunable error feedback structure and a novel and more cost-effective digital power ramp generator, were developed.reviewe

Synthetic Aperture Radar Image Formation and Processing on an MPSoC

Satellite remote sensing acquisitions are usually processed after downlink to a ground station. The satellite travel time to the ground station adds to the total latency, increasing the time until a user can obtain the processing results. Performing the processing and information extraction onboard of the satellite can significantly reduce this time. In this study, synthetic aperture radar (SAR) image formation as well as ship detection and extreme weather detection were implemented in a multiprocessor system on a chip (MPSoC). Processing steps with high computational complexity were ported to run on the programmable logic (PL), achieving significant speed-up by implementing a high degree of parallelization and pipelining as well as efficient memory accesses. Steps with lower complexity run on the processing system (PS), allowing for higher flexibility and reducing the need for resources in the PL. The achieved processing times for an area covering 375 km2 were approximately 4 s for image formation, 16 s for ship detection, and 31 s for extreme weather detection. These evelopments combined with new downlink concepts for low-rate information data streams show that the provision of satellite remote sensing results to end users in less than 5 min after acquisition is possible using an adequately equipped satellite

Development of a Multichannel Wideband Radar Demonstrator

With the rise of software defined radios (SDR) and the trend towards integrating more RF components into MMICs the cost and complexity of multichannel radar develop- ment has gone down. High-speed RF data converters have seen continuous increases in both sampling rate and resolution, further rendering a growing subset of components in an RF chain unnecessary. A recent development in this trend is the Xilinx RF- SoC, which integrates multiple high speed data converters into the same package as an FPGA. The Center for Remote Sensing of Ice Sheets (CReSIS) is regularly upgrading its suite of sensor platforms spanning from HF depth sounders to Ka band altimeters. A radar platform was developed around the RFSoC to demonstrate the capabilities of the chip when acting as a digital backend and evaluate its role in future radar designs at CReSIS. A new ultra-wideband (UWB) FMCW RF frontend was designed that con- sists of multiple transmit and receive modules with a 6 GHz bandwidth centered at 5 GHz. An antenna array was constructed out of Vivaldi elements to validate radar system performance. Firmware developed for the RFSoC enables radar features such as beam forming, frequency notching, dynamic stretch processing, and variable gain correction. The feature set presented here may prove useful in future sensor platforms used for the remote sensing of snow, soil moisture, or crop canopies