Expansion of CMOS array design techniques

The important features of the multiport (double entry) automatic placement and routing programs for standard cells are described. Measured performance and predicted performance were compared for seven CMOS/SOS array types and hybrids designed with the high speed CMOS/SOS cell family. The CMOS/SOS standard cell data sheets are listed and described

Implementation of Large Scale Integrated (LSI) circuit design software

Portions of the Computer Aided Design and Test system, a collection of Large Scale Integrated (LSI) circuit design programs were modified and upgraded. Major modifications were made to the Mask Analysis Program in the form of additional operating commands and file processing options. Modifications were also made to the Artwork Interactive Design System to correct some deficiencies in the original program as well as to add several new command features related to improving the response of AIDS when dealing with large files. The remaining work was concerned with updating various programs within CADAT to incorporate the silicon on sapphire silicon gate technology

In-flight maintenance study Final report

Sample system analysis, MF requirements, redesign, and packaging desig

大規模システムLSI設計のための統一的ハードウェア・ソフトウェア協調検証手法

Currently, the complexity of embedded LSI system is growing faster than the productivity of system design. This trend results in a design productivity gap, particularly in tight development time. Since the verification task takes bigger part of development task, it becomes a major challenge in LSI system design. In order to guarantee system reliability and quality of results (QoR), verifying large coverage of system functionality requires huge amount of relevant test cases and various scenario of evaluations. To overcome these problems, verification methodology is evolving toward supporting higher level of design abstraction by employing HW-SW co-verification. In this study, we present a novel approach for verification LSI circuit which is called as unified HW/SW co-verification framework. The study aims to improve design efficiency while maintains implementation consistency in the point of view of system-level performance. The proposed data-driven simulation and flexible interface of HW and SW design become the backbone of verification framework. In order to avoid time consuming, prone error, and iterative design spin-off in a large team, the proposed framework has to support multiple design abstractions. Hence, it can close the loop of design, exploration, optimization, and testing. Furthermore, the proposed methodology is also able to co-operate with system-level simulation in high-level abstraction, which is easy to extend for various applications and enables fast-turn around design modification. These contributions are discussed in chapter 3. In order to show the effectiveness and the use-cases of the proposed verification framework, the evaluation and metrics assessments of Very High Throughput wireless LAN system design are carried out. Two application examples are provided. The first case in chapter 4 is intended for fast verification and design exploration of large circuit. The Maximum Likelihood Detection (MLD) MIMO decoder is considered as Design Under Test (DUT). The second case, as presented in chapter 5, is the evaluation for system-level simulation. The full transceiver system based on IEEE 802.11ac standard is employed as DUT. Experimental results show that the proposed verification approach gives significant improvements of verification time (e.g. up to 10,000 times) over the conventional scheme. The proposed framework is also able to support various schemes of system level evaluations and cross-layer evaluation of wireless system.九州工業大学博士学位論文 学位記番号：情工博甲第328号 学位授与年月日：平成29年6月30日1 Introduction|2 Design and Verification in LSI System Design|3 Unified HW/SW Co-verification Methodology|4 Fast Co-verification and Design Exploration in Complex Circuits|5 Unified System Level Simulator for Very High Throughput Wireless Systems|6 Conclusion and Future Work九州工業大学平成29年

Autonomous spacecraft maintenance study group

A plan to incorporate autonomous spacecraft maintenance (ASM) capabilities into Air Force spacecraft by 1989 is outlined. It includes the successful operation of the spacecraft without ground operator intervention for extended periods of time. Mechanisms, along with a fault tolerant data processing system (including a nonvolatile backup memory) and an autonomous navigation capability, are needed to replace the routine servicing that is presently performed by the ground system. The state of the art fault handling capabilities of various spacecraft and computers are described, and a set conceptual design requirements needed to achieve ASM is established. Implementations for near term technology development needed for an ASM proof of concept demonstration by 1985, and a research agenda addressing long range academic research for an advanced ASM system for 1990s are established

Advanced electrochemical depolarized concentrator cell development

An advanced electrochemical depolarized carbon dioxide concentrator subsystem, to collect and concentrate metabolically produced CO2 for subsequent O2 recovery in spacecraft, is discussed

Advanced water iodinating system

Potable water stores aboard manned spacecraft must remain sterile. Suitable sterilization techniques are needed to prevent microbial growth. The development of an advanced water iodinating system for possible application to the shuttle orbiter and other advanced spacecraft, is considered. The AWIS provides a means of automatically dispensing iodine and controlling iodination levels in potable water stores. In a recirculation mode test, simulating application of the AWIS to a water management system of a long term six man capacity space mission, noniodinated feed water flowing at 32.2 cu cm min was iodinated to 5 + or - ppm concentrations after it was mixed with previously iodinated water recirculating through a potable water storage tank. Also, the AWIS was used to successfully demonstrate its capability to maintain potable water at a desired I2 concentration level while circulating through the water storage tank, but without the addition of noniodinated water

Design verification test matrix development for the STME thrust chamber assembly

This report presents the results of the test matrix development for design verification at the component level for the National Launch System (NLS) space transportation main engine (STME) thrust chamber assembly (TCA) components including the following: injector, combustion chamber, and nozzle. A systematic approach was used in the development of the minimum recommended TCA matrix resulting in a minimum number of hardware units and a minimum number of hot fire tests

Development of a static feed water electrolysis system

A one person level oxygen generation subsystem was developed and production of the one person oxygen metabolic requirements, 0.82 kg, per day was demonstrated without the need for condenser/separators or electrolyte pumps. During 650 hours of shakedown, design verification, and endurance testing, cell voltages averaged 1.62 V at 206 mA/sq cm and at average operating temperature as low as 326 K, virtually corresponding to the state of the art performance previously established for single cells. This high efficiency and low waste heat generation prevented maintenance of the 339 K design temperature without supplemental heating. Improved water electrolysis cell frames were designed, new injection molds were fabricated, and a series of frames was molded. A modified three fluid pressure controller was developed and a static feed water electrolysis that requires no electrolyte in the static feed compartment was developed and successfully evaluated