Design and Implementation of High-Efficiency, Lightweight, System-Friendly Solid-State Circuit Breaker

Direct current (DC) distribution system has shown potential over the alternative current (AC) distribution system in some application scenarios, e.g., electrified transportation, renewable energy, data center, etc. Because of the fast response speed, DC solid-state circuit breaker (SSCB) becomes a promising technology for the future power electronics intensive DC energy system with fault-tolerant capability. First, a thorough literature survey is performed to review the DC-SSCB technology. The key components for DC-SSCB, including power semiconductors, topologies, energy absorption units, and fault detection circuits, are studied. It is observed that the prior studies mainly focus on the basic interruption capability of the DC-SSCB. There are not so many studies on SSCB’s size optimization or system-friendly functions. Second, an insulated gate bipolar transistor (IGBT) based lightweight SSCB is proposed. With the reduced gate voltage, the proposed SSCB can limit the peak fault current without the bulky and heavy fault current limiting the inductor, which exists in the conventional SSCB circuit. Thus, the specific power density of the SSCB is substantially improved compared with the conventional design. Meanwhile, to understand the impact of different design parameters on the performance of SSCB, an analytical model is built to establish the relationship between SSCB dynamic performance and operating conditions considering the key components and circuit parasitics. Simulation and test results demonstrate the accuracy of the proposed model. To limit the fault current with the proposed SSCB without a current limiting inductor, power semiconductors need to operate in the active region temporarily. During this interval, a severe voltage oscillation has been observed experimentally, leading to the DC-SSCB overstress and eventually the failure. A detailed MATLAB/Simulink model is built to understand the mechanism causing the voltage oscillation. Three suppression methods using enhanced gate drive circuitry are proposed and compared. Test results based on a 2kV/1kA SSCB prototype demonstrate the effectiveness of the proposed oscillation mitigation method and the accuracy of the derived model. Meanwhile, when the system fault impedance is close to zero (e.g., high di/dt), the influence of the parasitic inductance contributed by interconnection (e.g., bus bar, module package, etc.) cannot be neglected. To study the influence of the bus bar connections on SSCB with high di/dt, a Q3D extractor is adopted to extract the parasitic parameters of the SSCB and understand the influence of different bus bar connections. A vertical bus bar is proposed to suppress the side effect and verified by the Q3D extractor and experimental results. Finally, a system-friendly SSCB is demonstrated. The proposed gate drive enables the SSCB to operate in the current limitation mode for the overcurrent limitation. The current limitation level and limitation time can be tuned by the gate drive. Then, this dissertation provides an all-in-one solution with integrated circuitries as the fault detector, actuator for the semiconductor’s operating status regulation, and coordinated control. This allows the developed SSCB to limit system fault current not exceeding short-circuit current rating (SCCR) and also take different responses under different fault cases. The feasibility and the effectiveness of the proposed system-friendly SSCB are validated with experimental results based on a 200V/10A SSCB demonstrator