Null Convention Logic applications of asynchronous design in nanotechnology and cryptographic security

This dissertation presents two Null Convention Logic (NCL) applications of asynchronous logic circuit design in nanotechnology and cryptographic security. The first application is the Asynchronous Nanowire Reconfigurable Crossbar Architecture (ANRCA); the second one is an asynchronous S-Box design for cryptographic system against Side-Channel Attacks (SCA). The following are the contributions of the first application: 1) Proposed a diode- and resistor-based ANRCA (DR-ANRCA). Three configurable logic block (CLB) structures were designed to efficiently reconfigure a given DR-PGMB as one of the 27 arbitrary NCL threshold gates. A hierarchical architecture was also proposed to implement the higher level logic that requires a large number of DR-PGMBs, such as multiple-bit NCL registers. 2) Proposed a memristor look-up-table based ANRCA (MLUT-ANRCA). An equivalent circuit simulation model has been presented in VHDL and simulated in Quartus II. Meanwhile, the comparison between these two ANRCAs have been analyzed numerically. 3) Presented the defect-tolerance and repair strategies for both DR-ANRCA and MLUT-ANRCA. The following are the contributions of the second application: 1) Designed an NCL based S-Box for Advanced Encryption Standard (AES). Functional verification has been done using Modelsim and Field-Programmable Gate Array (FPGA). 2) Implemented two different power analysis attacks on both NCL S-Box and conventional synchronous S-Box. 3) Developed a novel approach based on stochastic logics to enhance the resistance against DPA and CPA attacks. The functionality of the proposed design has been verified using an 8-bit AES S-box design. The effects of decision weight, bitstream length, and input repetition times on error rates have been also studied. Experimental results shows that the proposed approach enhances the resistance to against the CPA attack by successfully protecting the hidden key --Abstract, page iii

On Finding a Defect-free Component in Nanoscale Crossbar Circuits

AbstractWe propose a technique for the analysis of manufacturing yield of nano-crossbar architectures for different values of defect percentage and crossbar-size. We provide an estimate of the minimum-size crossbar to be fabricated wherein a defect-free crossbar of a given size can always be found with a guaranteed yield. Our technique is based on logical merging of two defective rows (or two columns) that emulate a defect-free row (or column). Experimental results show that the proposed method provides higher defect-tolerance compared to that of previous techniques

On the production testing of analog and digital circuits

This thesis focuses on the production testing of Analog and Digital circuits. First, it addresses the issue of finding a high coverage minimum test set for the second generation current conveyor as this was not tackled before. The circuit under test is used in active capacitance multipliers, V-I scalar circuits, Biquadratic filters and many other applications. This circuit is often used to implement voltage followers, current followers and voltage to current converters. Five faults are assumed per transistor. It is shown that, to obtain 100% fault coverage, the CCII has to be operated in voltage to current converter mode. Only two test values are required to obtain this fault coverage. Additionally, the thesis focuses on the production testing of Memristor Ratioed Logic (MRL) gates because this was not studied before. MRL is a family that uses memristors along with CMOS inverters to design logic gates. Two-input NAND and NOR gates are investigated using the stuck at fault model for the memristors and the five-fault model for the transistors. It is shown that in order to obtain full coverage for the MRL NAND and NOR gates, two solutions are proposed. The first is the usage of scaled input voltages to prevent the output from falling in the undefined region. The second proposed solution is changing the switching threshold VM of the CMOS inverter. In addition, it is shown that test speed and order should be taken into consideration. It is proven that three ordered test vectors are needed for full coverage in MRL NAND and NOR gates, which is different from the 100% coverage test set in the conventional NAND and NOR CMOS designs

Design, Test, and Repair of MLUT (Memristor Look-Up Table) Based Asynchronous Nanowire Reconfigurable Crossbar Architecture

The recently proposed nanoscale asynchronous crossbar architecture based on memristor-based look up table (MLUT) combines the advantages of nanoscale memristor crossbar technology and clockless logic paradigm for viable nanoscale computing. Potential technical merits of the proposed MLUT architecture includes: 1) better manufacturability due to structural simplicity and regularity; 2) improved robustness over PVT (process-voltage-temperature) variations; 3) event-driven low-power/noise asynchronous operation; and 4) encoding-level logic inversion. In spite of having numerous merits over the clocked counterparts and previous asynchronous designs, it is bound to have inevitable defects and faults due to nondeterministic and unconventional nanoscale assembly and operation. In order to overcome defect issues in the proposed MLUT-based nanoscale asynchronous crossbar architecture, there is a need to develop efficient design, test, and repair techniques. Typical approach so far has been to test every crosspoint on each crossbar MLUT exhaustively; this is not only laborious but is also prohibitively time and space consuming for designs involving large number of MLUTs. This paper introduces a novel testing scheme based on \u27Divide and Conquer\u27 approach to efficiently locate the defective memristors in a MLUT. The proposed testing scheme leverages upon a special current additive property of the memristor-based multiplexer. It performs binary isolation of regions, reducing the search space by half whenever applicable. Numerical simulations clearly demonstrate that the approach is generic, deterministic, and scalable. A faster MLUT programming technique and a repair technique utilizing partially defective MLUTs are also proposed and extensively validated through parametric simulations