Single fault detection in combinational logic circuits

The material in this paper is divided into the following four chapters for convenience. Chapter 1 explains, how the idea of fault testing changed from testing the machine instructions to testing the hardware in logic circuits. Chapters 2, 3 and 4 present the different approaches considered, namely: 1. Path sensitizing and D-Algorithm method. 2. Tabular method. 3. Boolean difference method

On testing concurrent systems through contexts of queues

Concurrent systems, including asynchronous circuits, computer networks, and multi-threaded programs, have important applications, but they are also very complex and expensive to test. This thesis studies how to test concurrent systems through contexts consisting of queues. Queues, modeling buffers and communication delays, are an integral part of the test settings for concurrent systems. However, queues can also distort the behavior of the concurrent system as observed by the tester, so one should take into account the queues when defining conformance relations or deriving tests. On the other hand, queues can cause state explosion, so one should avoid testing them if they are reliable or have already been tested. To solve these problems, we propose two different solutions. The first solution is to derive tests using some test selection criteria such as test purposes, fault coverage, and transition coverage. The second solution is to compensate for the problems caused by the queues so that testers do not discern the presence of the queues in the first place. Unifying the presentation of the two solutions, we consider in a general testing framework partial specifications, various contexts, and a hierarchy of conformance relations. Case studies on test derivation for asynchronous circuits, communication protocols, and multi-threaded programs are presented to demonstrate the applications of the results

Techniques for the realization of ultra- reliable spaceborne computer Final report

Bibliography and new techniques for use of error correction and redundancy to improve reliability of spaceborne computer