Dynamic Voltage Scaling Aware Delay Fault Testing

The application of Dynamic Voltage Scaling (DVS) to reduce energy consumption may have a detrimental impact on the quality of manufacturing tests employed to detect permanent faults. This paper analyses the influence of different voltage/frequency settings on fault detection within a DVS application. In particular, the effect of supply voltage on different types of delay faults is considered. This paper presents a study of these problems with simulation results. We have demonstrated that the test application time increases as we reduce the test voltage. We have also shown that for newer technologies we do not have to go to very low voltage levels for delay fault testing. We conclude that it is necessary to test at more than one operating voltage and that the lowest operating voltage does not necessarily give the best fault cover

Product assurance technology for custom LSI/VLSI electronics

The technology for obtaining custom integrated circuits from CMOS-bulk silicon foundries using a universal set of layout rules is presented. The technical efforts were guided by the requirement to develop a 3 micron CMOS test chip for the Combined Release and Radiation Effects Satellite (CRRES). This chip contains both analog and digital circuits. The development employed all the elements required to obtain custom circuits from silicon foundries, including circuit design, foundry interfacing, circuit test, and circuit qualification

Product assurance technology for procuring reliable, radiation-hard, custom LSI/VLSI electronics

Advanced measurement methods using microelectronic test chips are described. These chips are intended to be used in acquiring the data needed to qualify Application Specific Integrated Circuits (ASIC's) for space use. Efforts were focused on developing the technology for obtaining custom IC's from CMOS/bulk silicon foundries. A series of test chips were developed: a parametric test strip, a fault chip, a set of reliability chips, and the CRRES (Combined Release and Radiation Effects Satellite) chip, a test circuit for monitoring space radiation effects. The technical accomplishments of the effort include: (1) development of a fault chip that contains a set of test structures used to evaluate the density of various process-induced defects; (2) development of new test structures and testing techniques for measuring gate-oxide capacitance, gate-overlap capacitance, and propagation delay; (3) development of a set of reliability chips that are used to evaluate failure mechanisms in CMOS/bulk: interconnect and contact electromigration and time-dependent dielectric breakdown; (4) development of MOSFET parameter extraction procedures for evaluating subthreshold characteristics; (5) evaluation of test chips and test strips on the second CRRES wafer run; (6) two dedicated fabrication runs for the CRRES chip flight parts; and (7) publication of two papers: one on the split-cross bridge resistor and another on asymmetrical SRAM (static random access memory) cells for single-event upset analysis

Polymer Microring Coupled-Resonator Optical Waveguides

We present measurements of the transmission and dispersion properties of coupled-resonator optical waveguides (CROWs) consisting of weakly coupled polymer microring resonators. The fabrication and the measurement methods of the CROWs are discussed as well. The experimental results agree well with the theoretical loss, waveguide dispersion, group delay, group velocity, and group-velocity dispersion (GVD). The intrinsic quality factors of the microrings were about 1.5 times 10^4 to 1.8 times 10^4, and group delays greater than 100 ps were measured with a GVD between -70 and 100 ps/(nm x resonator). With clear and simple spectral responses and without a need for the tuning of the resonators, the polymer microring CROWs demonstrate the practicability of using a large number of microresonators to control the propagation of optical waves

Phase Locked Loop Test Methodology

Phase locked loops are incorporated into almost every large-scale mixed signal and digital system on chip (SOC). Various types of PLL architectures exist including fully analogue, fully digital, semi-digital, and software based. Currently the most commonly used PLL architecture for SOC environments and chipset applications is the Charge-Pump (CP) semi-digital type. This architecture is commonly used for clock synthesis applications, such as the supply of a high frequency on-chip clock, which is derived from a low frequency board level clock. In addition, CP-PLL architectures are now frequently used for demanding RF (Radio Frequency) synthesis, and data synchronization applications. On chip system blocks that rely on correct PLL operation may include third party IP cores, ADCs, DACs and user defined logic (UDL). Basically, any on-chip function that requires a stable clock will be reliant on correct PLL operation. As a direct consequence it is essential that the PLL function is reliably verified during both the design and debug phase and through production testing. This chapter focuses on test approaches related to embedded CP-PLLs used for the purpose of clock generation for SOC. However, methods discussed will generally apply to CP-PLLs used for other applications

CMOL: Second Life for Silicon?

This report is a brief review of the recent work on architectures for the prospective hybrid CMOS/nanowire/ nanodevice ("CMOL") circuits including digital memories, reconfigurable Boolean-logic circuits, and mixed-signal neuromorphic networks. The basic idea of CMOL circuits is to combine the advantages of CMOS technology (including its flexibility and high fabrication yield) with the extremely high potential density of molecular-scale two-terminal nanodevices. Relatively large critical dimensions of CMOS components and the "bottom-up" approach to nanodevice fabrication may keep CMOL fabrication costs at affordable level. At the same time, the density of active devices in CMOL circuits may be as high as 1012 cm2 and that they may provide an unparalleled information processing performance, up to 1020 operations per cm2 per second, at manageable power consumption.Comment: Submitted on behalf of TIMA Editions (http://irevues.inist.fr/tima-editions

Early detection of capping risk in pharmaceutical compacts

Capping is a common mechanical defect in tablet manufacturing, exhibited during or after the compression process. Predicting tablet capping in terms of process variables (e.g. compaction pressure and speed) and formulation properties is essential in pharmaceutical industry. In current work, a non-destructive contact ultrasonic approach for detecting capping risk in the pharmaceutical compacts prepared under various compression forces and speeds is presented. It is shown that the extracted mechanical properties can be used as early indicators for invisible capping (prior to visible damage). Based on the analysis of X-ray cross-section images and a large set of waveform data, it is demonstrated that the mechanical properties and acoustic wave propagation characteristics is significantly modulated by the tablet’s internal cracks and capping at higher compaction speeds and pressures. In addition, the experimentally extracted properties were correlated to the directly-measured porosity and tensile strength of compacts of Pearlitol®, Anhydrous Mannitol and LubriTose® Mannitol, produced at two compaction speeds and at three pressure levels. The effect compaction speed and pressure on the porosity and tensile strength of the resulting compacts is quantified, and related to the compact acoustic characteristics and mechanical properties. The detailed experimental approach and reported wave propagation data could find key applications in determining the bounds of manufacturing design spaces in the development phase, predicting capping during (continuous) tablet manufacturing, as well as online monitoring of tablet mechanical integrity and reducing batch-to-batch end-product quality variations