28 research outputs found
Excitable Delaunay triangulations
In an excitable Delaunay triangulation every node takes three states
(resting, excited and refractory) and updates its state in discrete time
depending on a ratio of excited neighbours. All nodes update their states in
parallel. By varying excitability of nodes we produce a range of phenomena,
including reflection of excitation wave from edge of triangulation, backfire of
excitation, branching clusters of excitation and localized excitation domains.
Our findings contribute to studies of propagating perturbations and waves in
non-crystalline substrates
Cellular Structures for Computation in the Quantum Regime
We present a new cellular data processing scheme, a hybrid of existing
cellular automata (CA) and gate array architectures, which is optimized for
realization at the quantum scale. For conventional computing, the CA-like
external clocking avoids the time-scale problems associated with ground-state
relaxation schemes. For quantum computing, the architecture constitutes a novel
paradigm whereby the algorithm is embedded in spatial, as opposed to temporal,
structure. The architecture can be exploited to produce highly efficient
algorithms: for example, a list of length N can be searched in time of order
cube root N.Comment: 11 pages (LaTeX), 3 figure
Fault tolerance issues in nanoelectronics
The astonishing success story of microelectronics cannot go on indefinitely. In fact, once
devices reach the few-atom scale (nanoelectronics), transient quantum effects are expected
to impair their behaviour. Fault tolerant techniques will then be required. The aim of this
thesis is to investigate the problem of transient errors in nanoelectronic devices. Transient
error rates for a selection of nanoelectronic gates, based upon quantum cellular automata
and single electron devices, in which the electrostatic interaction between electrons is used
to create Boolean circuits, are estimated. On the bases of such results, various fault tolerant
solutions are proposed, for both logic and memory nanochips. As for logic chips, traditional
techniques are found to be unsuitable. A new technique, in which the voting approach of
triple modular redundancy (TMR) is extended by cascading TMR units composed of
nanogate clusters, is proposed and generalised to other voting approaches. For memory
chips, an error correcting code approach is found to be suitable. Various codes are
considered and a lookup table approach is proposed for encoding and decoding. We are
then able to give estimations for the redundancy level to be provided on nanochips, so as to
make their mean time between failures acceptable. It is found that, for logic chips, space
redundancies up to a few tens are required, if mean times between failures have to be of the
order of a few years. Space redundancy can also be traded for time redundancy. As for
memory chips, mean times between failures of the order of a few years are found to imply
both space and time redundancies of the order of ten
Performance analysis of fault-tolerant nanoelectronic memories
Performance growth in microelectronics, as described by Moore’s law, is steadily
approaching its limits. Nanoscale technologies are increasingly being explored as a
practical solution to sustaining and possibly surpassing current performance trends of
microelectronics. This work presents an in-depth analysis of the impact on performance,
of incorporating reliability schemes into the architecture of a crossbar molecular switch
nanomemory and demultiplexer. Nanoelectronics are currently in their early stages, and
so fabrication and design methodologies are still in the process of being studied and
developed. The building blocks of nanotechnology are fabricated using bottom-up
processes, which leave them highly susceptible to defects. Hence, it is very important that
defect and fault-tolerant schemes be incorporated into the design of nanotechnology
related devices.
In this dissertation, we focus on the study of a novel and promising class of
computer chip memories called crossbar molecular switch memories and their
demultiplexer addressing units. A major part of this work was the design of a defect and
fault tolerance scheme we called the Multi-Switch Junction (MSJ) scheme. The MSJ scheme takes advantage of the regular array geometry of the crossbar nanomemory to
create multiple switches in the fabric of the crossbar nanomemory for the storage of a
single bit.
Implementing defect and fault tolerant schemes come at a performance cost to the
crossbar nanomemory; the challenge becomes achieving a balance between device
reliability and performance. We have studied the reliability induced performance penalties
as they relate to the time (delay) it takes to access a bit, and the amount of power
dissipated by the process. Also, MSJ was compared to the banking and error correction
coding fault tolerant schemes. Studies were also conducted to ascertain the potential
benefits of integrating our MSJ scheme with the banking scheme. Trade-off analysis
between access time delay, power dissipation and reliability is outlined and presented in
this work.
Results show the MSJ scheme increases the reliability of the crossbar
nanomemory and demultiplexer. Simulation results also indicated that MSJ works very
well for smaller nanomemory array sizes, with reliabilities of 100% for molecular switch
failure rates in the 10% or less range
Fault and Defect Tolerant Computer Architectures: Reliable Computing With Unreliable Devices
This research addresses design of a reliable computer from unreliable device technologies. A system architecture is developed for a fault and defect tolerant (FDT) computer. Trade-offs between different techniques are studied and yield and hardware cost models are developed. Fault and defect tolerant designs are created for the processor and the cache memory. Simulation results for the content-addressable memory (CAM)-based cache show 90% yield with device failure probabilities of 3 x 10(-6), three orders of magnitude better than non fault tolerant caches of the same size. The entire processor achieves 70% yield with device failure probabilities exceeding 10(-6). The required hardware redundancy is approximately 15 times that of a non-fault tolerant design. While larger than current FT designs, this architecture allows the use of devices much more likely to fail than silicon CMOS. As part of model development, an improved model is derived for NAND Multiplexing. The model is the first accurate model for small and medium amounts of redundancy. Previous models are extended to account for dependence between the inputs and produce more accurate results
Methods and architectures based on modular redundancy for fault-tolerant combinational circuits
Dans cette thèse, nous nous intéressons à la recherche d architectures fiables pour les circuits logiques. Par fiable , nous entendons des architectures permettant le masquage des fautes et les rendant de ce fait tolérantes" à ces fautes. Les solutions pour la tolérance aux fautes sont basées sur la redondance, d où le surcoût qui y est associé. La redondance peut être mise en oeuvre de différentes manières : statique ou dynamique, spatiale ou temporelle. Nous menons cette recherche en essayant de minimiser tant que possible le surcoût matériel engendré par le mécanisme de tolérance aux fautes. Le travail porte principalement sur les solutions de redondance modulaire, mais certaines études développées sont beaucoup plus générales.In this thesis, we mainly take into account the representative technique Triple Module Redundancy (TMR) as the reliability improvement technique. A voter is an necessary element in this kind of fault-tolerant architectures. The importance of reliability in majority voter is due to its application in both conventional fault-tolerant design and novel nanoelectronic systems. The property of a voter is therefore a bottleneck since it directly determines the whole performance of a redundant fault-tolerant digital IP (such as a TMR configuration). Obviously, the efficacy of TMR is to increase the reliability of digital IP. However, TMR sometimes could result in worse reliability than a simplex function module could. A better understanding of functional and signal reliability characteristics of a 3-input majority voter (majority voting in TMR) is studied. We analyze them by utilizing signal probability and boolean difference. It is well known that the acquisition of output signal probabilities is much easier compared with the obtention of output reliability. The results derived in this thesis proclaim the signal probability requirements for inputs of majority voter, and thereby reveal the conditions that TMR technique requires. This study shows the critical importance of error characteristics of majority voter, as used in fault-tolerant designs. As the flawlessness of majority voter in TMR is not true, we also proposed a fault-tolerant and simple 2-level majority voter structure for TMR. This alternative architecture for majority voter is useful in TMR schemes. The proposed solution is robust to single fault and exceeds those previous ones in terms of reliability.PARIS-Télécom ParisTech (751132302) / SudocSudocFranceF