Design of TSV-sharing topologies for cost-effective 3D networks-on-chip

The Through-Silicon Via (TSV) technology has led to major breakthroughs in 3D stacking by providing higher speed and bandwidth, as well as lower power dissipation for the inter-layer communication. However, the current TSV fabrication suffers from a considerable area footprint and yield loss. Thus, it is necessary to restrict the number of TSVs in order to design cost-effective 3D on-chip networks. This critical issue can be addressed by clustering the network such that all of the routers within each cluster share a single TSV pillar for the vertical packet transmission. In some of the existing topologies, additional cluster routers are augmented into the mesh structure to handle the shared TSVs. However, they impose either performance degradation or power/area overhead to the system. Furthermore, the resulting architecture is no longer a mesh. In this paper, we redefine the clusters by replacing some routers in the mesh with the cluster routers, such that the mesh structure is preserved. The simulation results demonstrate a better equilibrium between performance and cost, using the proposed models

Global Adaptation Controlled by an Interactive Consistency Protocol

Static schedules for systems can lead to an inefficient usage of the resources, because the system’s behavior cannot be adapted at runtime. To improve the runtime system performance in current time-triggered Multi-Processor System on Chip (MPSoC), a dynamic reaction to events is performed locally on the cores. The effects of this optimization can be increased by coordinating the changes globally. To perform such global changes, a consistent view on the system state is needed, on which to base the adaptation decisions. This paper proposes such an interactive consistency protocol with low impact on the system w.r.t. latency and overhead. We show that an energy optimizing adaptation controlled by the protocol can enable a system to save up to 43% compared to a system without adaptation

Efficient router design for network on chip

A Network-on-chip (NoC) is a new paradigm in complex system-on-chip (SoC) designs that provide efficient on chip communication networks. It allows scalable communication and allows decoupling of communication and computation. The data is routed through the networks in terms of packets. The routing of data is mainly done by routers. So the architecture of router must be an efficient one with a lower latency and higher throughput. In this project we designed, implemented and analyzed three different router architectures for a network on chip communication. The routers have five ports, four ports connected to other ports in four different directions and the fifth port connected to the processing element through a network interface. The first architecture is a basic router with demultiplexer and scheduler. The second architecture consists of crossbar switch and arbiter. The third architecture uses the CDMA technology that is popular in wireless communication. The three architectures were analyzed for their performance in terms of delay, throughput and latency and we concluded that CDMA router performs better than the other two

Roteador memresistivo para redes-em-chip de sistema bioinspirados

TCC (graduação) - Universidade Federal de Santa Catarina, Campus Blumenau, Engenharia de Controle e Automação.Este estudo introduz o projeto de um roteador digital genérico voltado para sistemas bioinspirados, baseado na tecnologia dos memristors. O objetivo principal é explorar as propriedades dos memristors e avaliar sua viabilidade em circuitos digitais, particularmente em roteadores e memórias. Os memristors, dispositivos teorizados por Leon Chua em 1971, possuem a capacidade única de ajustar sua resistência com base no fluxo de carga mais recente que atravessa seus terminais. Neste projeto, utilizou-se memristors para armazenar informações e realizar operações lógicas, aproveitando-os no desenvolvimento de uma biblioteca de circuitos memresistiva. Durante a pesquisa demonstrou-se que o dispositivo idealizado por Chua (1971) não responde bem a aplicações multiníveis mais complexas, no entanto, para circuitos mais ‘leves’, apresentaram resultados satisfatórios, mas ainda inferiores em termos de ocupação de área e dissipação de energia quando comparados a tecnologias recentes, como QCA e SET. Ao final, ressaltou-se que o uso de memristors na criação de memórias SRAM se mostrou eficaz e vantajoso em relação às abordagens que dependem exclusivamente de transistores. Portanto, embora haja bastante espaço para melhorias, os memristors já demonstram um potencial para aprimorar a eficiência dos circuitos de memória num futuro próximo.This study introduces the design of a generic digital router targeted for bioinspired systems, based on memristor technology. The main objective is to explore the properties of memristors and assess their feasibility in digital circuits, particularly in routers and memories. Memristors, devices theorized by Leon Chua in 1971, possess the unique capability to adjust their resistance based on the most recent flow of charge passing through their terminals. In this project, memristors were used to store information and perform logical operations, leveraging them in the development of a memristive circuit library. Throughout the research, it was demonstrated that the device envisioned by Chua (1971) does not respond well to heavier multilevel applications; however, for lighter circuits, they yielded satisfactory results, albeit still inferior in terms of footprint and energy dissipation compared to recent technologies like QCA and SET. In conclusion, the use of memristors in SRAM memory creation proved effective and advantageous in comparison to approaches relying solely on transistors. Therefore, while there is ample room for improvement, memristors already demonstrate potential for enhancing memory circuit efficiency in the near future

Framework for simulation of fault tolerant heterogeneous multiprocessor system-on-chip

Due to the ever growing requirement in high performance data computation, current Uniprocessor systems fall short of hand to meet critical real-time performance demands in (i) high throughput (ii) faster processing time (iii) low power consumption (iv) design cost and time-to-market factors and more importantly (v) fault tolerant processing. Shifting the design trend to MPSOCs is a work-around to meet these challenges. However, developing efficient fault tolerant task scheduling and mapping techniques requires optimized algorithms that consider the various scenarios in Multiprocessor environments. Several works have been done in the past few years which proposed simulation based frameworks for scheduling and mapping strategies that considered homogenous systems and error avoidance techniques. However, most of these works inadequately describe today\u27s MPSOC trend because they were focused on the network domain and didn\u27t consider heterogeneous systems with fault tolerant capabilities; In order to address these issues, this work proposes (i) a performance driven scheduling algorithm (PD SA) based on simulated annealing technique (ii) an optimized Homogenous-Workload-Distribution (HWD) Multiprocessor task mapping algorithm which considers the dynamic workload on processors and (iii) a dynamic Fault Tolerant (FT) scheduling/mapping algorithm to employ robust application processing system. The implementation was accompanied by a heterogeneous Multiprocessor system simulation framework developed in systemC/C++. The proposed framework reads user data, set the architecture, execute input task graph and finally generate performance variables. This framework alleviates previous work issues with respect to (i) architectural flexibility in number-of-processors, processor types and topology (ii) optimized scheduling and mapping strategies and (iii) fault-tolerant processing capability focusing more on the computational domain; A set of random as well as application specific STG benchmark suites were run on the simulator to evaluate and verify the performance of the proposed algorithms. The simulations were carried out for (i) scheduling policy evaluation (ii) fault tolerant evaluation (iii) topology evaluation (iv) Number of processor evaluation (v) Mapping policy evaluation and (vi) Processor Type evaluation. The results showed that PD scheduling algorithm showed marginally better performance than EDF with respect to utilization, Execution-Time and Power factors. The dynamic Fault Tolerant implementation showed to be a viable and efficient strategy to meet real-time constraints without posing significant system performance degradation. Torus topology gave better performance than Tile with respect to task completion time and power factors. Executing highly heterogeneous Tasks showed higher power consumption and execution time. Finally, increasing the number of processors showed a decrease in average Utilization but improved task completion time and power consumption; Based on the simulation results, the system designer can compare tradeoffs between a various design choices with respect to the performance requirement specifications. In general, designing an optimized Multiprocessor scheduling and mapping strategy with added fault tolerant capability will enable to develop efficient Multiprocessor systems which meet future performance goal requirements. This is the substance of this work