SLOPPGEN: A Problem Generator for the Two-Dimensional Rectangular Single Large Object Placement Problem With a Single Defect

In this paper, a problem generator for the Two-Dimensional Rectangular Single Large Object Placement Problem is presented. The parameters defining this problem are identified and described. The fea-tures of the problem generator are pointed out, and it is shown how the program can be used for the generation of reproducible random problem instances.two-dimensional cutting, defect, problem generator

Optimization strategy for actuator and sensor placement in active structural acoustic control

In active structural acoustic control the goal is to reduce the sound radiation of a structure by means of changing the vibrational behaviour of that structure. The performance of such an active control system is to a large extent determined by the locations of the actuators and sensors. In this work an approach is presented for the optimization of the actuator and sensor locations. The approach combines a numerical modelling technique, for predicting the control performance, and genetic optimization, to find the optimal actuator and sensor locations. The approach is tested for a setup consisting of clamped rectangular plate with a piezoelectric actuator and either structural or acoustic sensors. The results show that a control system with optimal actuator and sensor configuration outperforms an arbitrary chosen configuration in terms of reduction in radiated sound power

A new partitioning approach for layout synthesis from register-transfer netlists

Most of the IC today are described and documented using heiarchical netlists. In addition to gates, latches, and flip-flops, these netlists include sliceable register-transfer components such as registers, counters, adders, ALUs, shifters, register files, and multiplexers. Usually, these components are decomposed into basic gates, latches, and flip-flops, and are laid out using standard cells. The standard cell architecture requires excessive routing area, and does not exploit the bit-sliced nature of register-transfer components. In this paper, we present a new sliced-layout architecture to alleviate the preceding problems. We also describe partitioning algorithms that are used to generate the floorplan for this layout architecture. The partitioning algorithms not only select the best suited layout style for each component, but also consider critical paths, I/O pin locations, and connections between blocks. This approach improves the overall area utilization and minimizes the total wire length