A scalable multi-core architecture with heterogeneous memory structures for Dynamic Neuromorphic Asynchronous Processors (DYNAPs)

Neuromorphic computing systems comprise networks of neurons that use asynchronous events for both computation and communication. This type of representation offers several advantages in terms of bandwidth and power consumption in neuromorphic electronic systems. However, managing the traffic of asynchronous events in large scale systems is a daunting task, both in terms of circuit complexity and memory requirements. Here we present a novel routing methodology that employs both hierarchical and mesh routing strategies and combines heterogeneous memory structures for minimizing both memory requirements and latency, while maximizing programming flexibility to support a wide range of event-based neural network architectures, through parameter configuration. We validated the proposed scheme in a prototype multi-core neuromorphic processor chip that employs hybrid analog/digital circuits for emulating synapse and neuron dynamics together with asynchronous digital circuits for managing the address-event traffic. We present a theoretical analysis of the proposed connectivity scheme, describe the methods and circuits used to implement such scheme, and characterize the prototype chip. Finally, we demonstrate the use of the neuromorphic processor with a convolutional neural network for the real-time classification of visual symbols being flashed to a dynamic vision sensor (DVS) at high speed.Comment: 17 pages, 14 figure

Implementation of a Neuromorphic Development Platform with DANNA

Neuromorphic computing is the use of artificial neural networks to solve complex problems. The specialized computing field has been growing in interest during the past few years. Specialized hardware that function as neural networks can be utilized to solve specific problems unsuited for traditional computing architectures such as pattern classification and image recognition. However, these hardware platforms have neural network structures that are static, being limited to only perform a specific application, and cannot be used for other tasks. In this paper, the feasibility of a development platform utilizing a dynamic artificial neural network for researchers is discussed

Many-core and heterogeneous architectures: programming models and compilation toolchains

1noL'abstract è presente nell'allegato / the abstract is in the attachmentopen677. INGEGNERIA INFORMATInopartially_openembargoed_20211002Barchi, Francesc

Scalable High-Speed Communications for Neuromorphic Systems

Field-programmable gate arrays (FPGA), application-specific integrated circuits (ASIC), and other chip/multi-chip level implementations can be used to implement Dynamic Adaptive Neural Network Arrays (DANNA). In some applications, DANNA interfaces with a traditional computing system to provide neural network configuration information, provide network input, process network outputs, and monitor the state of the network. The present host-to-DANNA network communication setup uses a Cypress USB 3.0 peripheral controller (FX3) to enable host-to-array communication over USB 3.0. This communications setup has to run commands in batches and does not have enough bandwidth to meet the maximum throughput requirements of the DANNA device, resulting in output packet loss. Also, the FX3 is unable to scale to support larger single-chip or multi-chip configurations. To alleviate communication limitations and to expand scalability, a new communications solution is presented which takes advantage of the GTX/GTH high-speed serial transceivers found on Xilinx FPGAs. A Xilinx VC707 evaluation kit is used to prototype the new communications board. The high-speed transceivers are used to communicate to the host computer via PCIe and to communicate to the DANNA arrays with the link layer protocol Aurora. The new communications board is able to outperform the FX3, reducing the latency in the communication and increasing the throughput of data. This new communications setup will be used to further DANNA research by allowing the DANNA arrays to scale to larger sizes and for multiple DANNA arrays to be connected to a single communication board

Middleware and Services for Dynamic Adaptive Neural Network Arrays

Dynamic Adaptive Neural Network Arrays (DANNAs) are neuromorphic systems that exhibit spiking behaviors and can be designed using evolutionary optimization. Array elements are rapidly reconfigurable and can function as either neurons or synapses with programmable interconnections and parameters. Visualization applications can examine DANNA element connections, parameters, and functionality, and evolutionary optimization applications can utilize DANNA to speedup neural network simulations. To facilitate interactions with DANNAs from these applications, we have developed a language-agnostic application programming interface (API) that abstracts away low-level communication details with a DANNA and provides a high-level interface for reprogramming and controlling a DANNA. The library has also been designed in modules in order to adapt to future changes in the design of DANNA, including changes to the DANNA element design, DANNA communication protocol, and connection. In addition to communicating with DANNAs, it is also beneficial for applications to store networks with known functionality. Hence, a Representational State Transfer (REST) API with a MongoDB database back-end has been developed to encourage the collection and exploration of networks

AER-based robotic closed-loop control system

Address-Event-Representation (AER) is an asynchronous protocol for transferring the information of spiking neuro-inspired systems. Actually AER systems are able to see, to ear, to process information, and to learn. Regarding to the actuation step, the AER has been used for implementing Central Pattern Generator algorithms, but not for controlling the actuators in a closed-loop spike-based way. In this paper we analyze an AER based model for a real-time neuro-inspired closed-loop control system. We demonstrate it into a differential control system for a two-wheel vehicle using feedback AER information. PFM modulation has been used to power the DC motors of the vehicle and translation into AER of encoder information is also presented for the close-loop. A codesign platform (called AER-Robot), based into a Xilinx Spartan 3 FPGA and an 8051 USB microcontroller, with power stages for four DC motors has been used for the demonstrator.Junta de Andalucía P06-TIC-01417Ministerio de Educación y Ciencia TEC2006-11730-C03-0

A FPGA Spike-Based Robot Controlled with Neuro-inspired VITE

This paper presents a spike-based control system applied to a fixed robotic platform. Our aim is to take a step forward to a future complete spikes processing architecture, from vision to direct motor actuation. This paper covers the processing and actuation layer over an anthropomorphic robot. In this way, the processing layer uses the neuro-inspired VITE algorithm, for reaching a target, based on PFM taking advantage of spike system information: its frequency. Thus, all the blocks of the system are based on spikes. Each layer is implemented within a FPGA board and spikes communication is codified under the AER protocol. The results show an accurate behavior of the robotic platform with 6-bit resolution for a 130º range per joint, and an automatic speed control of the algorithm. Up to 96 motor controllers could be integrated in the same FPGA, allowing the positioning and object grasping by more complex anthropomorphic robots.Ministerio de Ciencia e Innovación TEC2009-10639-C04-02Ministerio de Economía y Competitividad TEC2012-37868-C04-0

Review of open neuromorphic architectures and a first integration in the RISC-V PULP platform

Although initially conceived as a tool to empower neuroscientific research by emulating and simulating the human brain, Spiking Neural Networks (SNNs), also known as third generation neural networks, are gaining popularity for their low-power and sparse data processing capabilities. These attributes are valuable for power-constrained edge and Internet of Things (IoT) applications. Several open-source FPGA and ASIC neuromorphic processors have been developed to explore thisfield, although they often require additional computing elements to manage data and communications. In this work, we review recent open-source neuromorphic architectures and the PULP ecosystem. We then present an integration of the ReckOn digitalneuromorphic processor with the PULPissimo RISC-V single core microcontroller to enable edge IoT applications. Our integrated design is validated through QuestaSim hardware simulation. Through this integration of low-power neuromorphic and RISC-V processors, we focus on the promising potential of SNNs for optimizing edge IoT systems constrained by power budgets and data sparsity