Loss compensation in Metamaterials through embedding of active transistor based negative differential resistance circuits

This paper presents an all-electronic approach for loss compensation in metamaterials. This is achieved by embedding active-transistors based negative differential resistance (NDR) circuits in each unit cell of the metamaterial lattice. NDR circuits provide tunable loss compensation over a broad frequency range limited only by the maximum operating frequency of transistors that is reaching terahertz values in newer semiconductor processes. Design, simulation and experimental results of metamaterials composed of split ring resonators (SRR) with and without loss compensation circuits are presented

Optimal design of a 2.4 GHz CMOS low noise amplifier

In most RF receivers, the Low Noise Amplifier (LNA) is normally the first component, whose performance is very critical. For the LNA architecture that uses source degeneration inductors and cascode topology, the performance depends largely on the performance of the inductors. All the parasitics associated with the inductors should be thoroughly analyzed and taken into consideration while designing the LNA. The work presented in this thesis can be broadly classified as follows: optimization of the LNA design with respect to all the parasitics associated with the on-chip spiral inductors, modeling high performance inductors, which are embedded in the silicon substrate and analysis of parasitic effects from the Electro Static Discharge (ESD) protection circuitry on the performance of the LNA. A methodology has been developed such that the LNA design can be optimized in the presence of an ESD protection circuitry in order to achieve the required input impedance match. This optimization procedure is presented for all possible placements of the ESD protection circuitry at the input of the LNA, that is, with respect to the gate inductor being realized on-chip or off-chip or a combination of on-chip and off-chip inductors. The thesis presents the procedure to vary the source inductance and gate inductance values in the presence of parasitic ESD capacitance in order to optimize LNA design such that the required input impedance match is maintained

Scaffolding Problem Solving with Embedded Examples to Promote Deep Learning

This study compared the relative utility of an intelligent tutoring system that uses procedure-based hints to a version that uses worked-out examples. The system, Andes, taught college level physics. In order to test which strategy produced better gains in competence, two versions of Andes were used: one offered participants graded hints and the other offered annotated, worked-out examples in response to their help requests. We found that providing examples was at least as effective as the hintsequences and was more efficient in terms of the number of problems it took to obtain the same level of mastery

Modeling and analysis of power processing systems: Feasibility investigation and formulation of a methodology

A review is given of future power processing systems planned for the next 20 years, and the state-of-the-art of power processing design modeling and analysis techniques used to optimize power processing systems. A methodology of modeling and analysis of power processing equipment and systems has been formulated to fulfill future tradeoff studies and optimization requirements. Computer techniques were applied to simulate power processor performance and to optimize the design of power processing equipment. A program plan to systematically develop and apply the tools for power processing systems modeling and analysis is presented so that meaningful results can be obtained each year to aid the power processing system engineer and power processing equipment circuit designers in their conceptual and detail design and analysis tasks