714 research outputs found

    Nonconvex Separable Programming Problem for Optimal Raw Material Mix in Flexible Polyurethane Foam Production

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    Nonconvex Separable Programming (NSP)  for selecting optimal raw material mix for flexible polyurethane foam production (FPFP) was developd. With unit cost function () as objective function;,Density(P1); compression set (P2); elongation(P3); hardness-index(P4) and tensile strength (P5) and other boundary conditions as constraints, an NSP foam raw material mix problem was defined and solved. Twelve existing formulation were used for validation .The cost and physical properties were determined and compared to the existing products using t-test. The optimal raw material mix 1.00, 0.4366, 0.0398, 0.0066, 0.0115, 0.0026, 0.0046 kg of polyol, toluene-di-isocynate, water, amine, silicone-oil, stannous-octoate and methylene-chloride respectively, were significantly different from  the existing formulations. The validated values of P1, P2, P3, P4, P5 from optimally formulated foams were 23.83kgm-3, 8.6%, 159.35%, 143.19N, and 117.33kNm-2, respectively and conformed to standard. The associated costs per metric tonne of the optimal mixes were lower than that of existing mixes.   Keywords: Polyurethane foam, Optimal-mix, Separable  programming , nonconvex, elongation

    Center for Aeronautics and Space Information Sciences

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    This report summarizes the research done during 1991/92 under the Center for Aeronautics and Space Information Science (CASIS) program. The topics covered are computer architecture, networking, and neural nets

    A Mechatronics System based on Feature Selection and AI for IoT Intrusion Detection Applications

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    In today's rapid development of the Internet, people's daily life has become easier, but on the other hand, people's privacy is also faced with potential threats if necessary security measures are not taken. To detect or stop cyberattacks in this area, network intrusion detection systems (IDS) can be equipped with machine learning algorithms to improve accuracy and speed. Recent research on intrusion and anomaly detection has shown that machine learning (ML) algorithms are widely used to detect malicious web traffic, using neural networks to learn models to visualize the sequence of connections between computers on a network. By analyzing and selecting the correct features, dense attacks can be detected more accurately, ultimately reducing misclassification rates and improving accuracy. In this study, we propose a Teacher-Student Feature Selection (TSFS) method that first uses the Isomap method to extract and select features in low dimensions and the best display, and then perform classification and the artificial neural MLP-Net for classification is used to minimize diagnostic errors. Although the teacher-student scheme is not new, to our knowledge, this is the first time this scheme has been used to select features in an intruder alert system. The proposed method can be used to select monitored and unmonitored features. The method is evaluated on different datasets and compared with the state-of-the-art feature selection methods available. The results show that the method performs better in classification, clustering and error detection. Furthermore, experimental evaluations show that the method is less sensitive to parameter selection

    A Mechatronics System based on Feature Selection and AI for IoT Intrusion Detection Applications

    Get PDF
    In today's rapid development of the Internet, people's daily life has become easier, but on the other hand, people's privacy is also faced with potential threats if necessary security measures are not taken. To detect or stop cyberattacks in this area, network intrusion detection systems (IDS) can be equipped with machine learning algorithms to improve accuracy and speed. Recent research on intrusion and anomaly detection has shown that machine learning (ML) algorithms are widely used to detect malicious web traffic, using neural networks to learn models to visualize the sequence of connections between computers on a network. By analyzing and selecting the correct features, dense attacks can be detected more accurately, ultimately reducing misclassification rates and improving accuracy. In this study, we propose a Teacher-Student Feature Selection (TSFS) method that first uses the Isomap method to extract and select features in low dimensions and the best display, and then perform classification and the artificial neural MLP-Net for classification is used to minimize diagnostic errors. Although the teacher-student scheme is not new, to our knowledge, this is the first time this scheme has been used to select features in an intruder alert system. The proposed method can be used to select monitored and unmonitored features. The method is evaluated on different datasets and compared with the state-of-the-art feature selection methods available. The results show that the method performs better in classification, clustering and error detection. Furthermore, experimental evaluations show that the method is less sensitive to parameter selection

    Neuroverkon inferenssi digitaalisessa signaalikäsittelyssä kovien reaaliaikavaatimusten alaisuudessa

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    The main objective of this thesis is to investigate how neural network inference can be efficiently implemented on a digital signal processor under hard real-time constraints from the execution speed point of view. Theories on digital signal processors and software optimization as well as neural networks are discussed. A neural network model for the specific use case is designed and a digital signal processor implementation is created based on the neural network model. A neural network model for the use case is created based on the data from the Matlab simulation model. The neural network model is trained and validated using the Python programming language with the Keras package. The neural network model is implemented on the CEVA-XC4500 digital signal processor. The digital signal processor implementation is written in C++ language with the processor specific vector-processing intrinsics. The neural network model is evaluated based on the model accuracy, precision, recall and f1-score. The model performance is compared to the conventional use case implementation by calculating 3GPP specified metrics of misdetection probability, false alarm rate and bit error rate. The execution speed of the digital signal processor implementation is evaluated with the CEVA integrated development environment profiling tool and also with the Lauterbach PowerTrace profiling module attached to the real base station product. Through this thesis, an optimized CEVA-XC4500 digital signal processor implementation was created for the specific neural network architecture. The optimized implementation showed to consume 88 percent less cycles than the conventional implementation. Also, the neural network model performance fulfills the 3GPP specification requirements.Tämän diplomityön tarkoituksena on tutkia miten neuroverkon inferenssi voidaan toteuttaa tehokkaasti digitaalisella signaaliprosessorilla suoritusnopeuden näkökulmasta, kun sovelluksella on kovat reaaliaikavaatimukset. Työssä käsitellään teoriaa digitaalisista signaaliprosessoreista, ohjelmistojen optimoinnista ja neuroverkoista. Työssä kehitetään neuroverkkomalli tiettyyn käyttötapaukseen, ja mallin pohjalta luodaan toteutus digitaaliselle signaaliprosessorille. Neuroverkkomalli luodaan Matlab-simulointimallin avulla kerätystä datasta. Neuroverkkomalli opetetaan ja varmennetaan Python-ohjelmointikiellellä ja Keras-paketilla. Neuroverkkomalli toteutetaan CEVA-XC4500 digitaaliselle signaaliprosessorille. Digitaalisen signaaliprosessorin toteutus kirjoitetaan C++-ohjelmointikielellä ja prosessorikohtaisilla vektorilaskentaoperaatioilla. Neuroverkkomalli varmennetaan mallin tarkkuuden, precision-arvon, recall-arvon ja f1-arvon perusteella. Mallin suorituskykyä verrataan käyttötapauksen tavanomaiseen toteutukseen laskemalla 3GPP-spesifikaation mukaiset mittarit virhehavaintotodennäköisyys, väärien hälytysten lukumäärä ja bittivirhemäärä. Suoritusnopeus määritetään sekä CEVA-ohjelmointiympäristön profilointityökalulla että tukiasematuotteeseen kytketyllä Lauterbach PowerTrace-yksiköllä. Työn tuloksena luotiin optimoitu CEVA-XC4500 digitaalinen signaaliprosessoritoteutus valitulle neuroverkkoarkkitehtuurille. Optimoitu toteutus kulutti 88% vähemmän laskentasyklejä kuin tavanomainen toteutus. Neuroverkkomalli täytti 3GPP-spesifikaation mukaiset vaatimukset

    Configurable analog hardware for neuromorphic Bayesian inference and least-squares solutions

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    Sparse approximation is a Bayesian inference program with a wide number of signal processing applications, such as Compressed Sensing recovery used in medical imaging. Previous sparse coding implementations relied on digital algorithms whose power consumption and performance scale poorly with problem size, rendering them unsuitable for portable applications, and a bottleneck in high speed applications. A novel analog architecture, implementing the Locally Competitive Algorithm (LCA), was designed and programmed onto a Field Programmable Analog Arrays (FPAAs), using floating gate transistors to set the analog parameters. A network of 6 coefficients was demonstrated to converge to similar values as a digital sparse approximation algorithm, but with better power and performance scaling. A rate encoded spiking algorithm was then developed, which was shown to converge to similar values as the LCA. A second novel architecture was designed and programmed on an FPAA implementing the spiking version of the LCA with integrate and fire neurons. A network of 18 neurons converged on similar values as a digital sparse approximation algorithm, with even better performance and power efficiency than the non-spiking network. Novel algorithms were created to increase floating gate programming speed by more than two orders of magnitude, and reduce programming error from device mismatch. A new FPAA chip was designed and tested which allowed for rapid interfacing and additional improvements in accuracy. Finally, a neuromorphic chip was designed, containing 400 integrate and fire neurons, and capable of converging on a sparse approximation solution in 10 microseconds, over 1000 times faster than the best digital solution.Ph.D
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