4 research outputs found
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Continuous time input pipeline ADCs
Analog-to-digital converters (ADCs) convert analog
continuous time signals into discrete time, digital format. One
precondition that must be met for conventional nyquist rate ADCs is
that the input signal must be suitably band-limited to an input
bandwidth less than the nyquist frequency. This mandates expensive
anti-alias filters which contribute to system noise and distortion
degradation. By choosing an OSR of 2 and adopting simple linear
phase filtering techniques, significant inherent anti-alias
filtering is achieved, avoiding the need for an explicit anti-alias
filter in many applications. Additionally the proposed continuous
time input pipeline ADC eases a number of other challenges present
in conventional switched capacitor ADCs:- sampled opamp noise
folding, sampling distortion, reduced ADC area, switched-capacitor
pipeline ADC input loading. Chapter 2 introduces the first
continuous time input pipeline ADC in the literature. This ADC,
while providing significant benefits, does not provide the inherent
filtering. Chapter 3 presents the first continuous time input
pipeline ADC with inherent anti-alias filtering
Design of Highly Efficient Analog-To-Digital Converters
The demand of higher data rates in communication systems is reflected in the constant evolution of communication standards. LTE-A and WiFi 802.11ac promote the use of carrier aggregation to increase the data rate of a wireless receiver. Recent DTV receivers promote the concept of full band capture to avoid the implementation of complex analog operations such as: filtering, equalization, modulation/demodulation, etc. All these operations can be implemented in a robust manner in the digital domain. Analog-to-Digital Converters (ADCs) are located at the heart of such architectures and require to have larger bandwidths and higher dynamic ranges. However, at higher data rates the power efficiency of ADCs tends to degrade. Moreover, while the scale of channel length in CMOS devices directly benefits the power, speed and area of digital circuits, analog circuits suffer from lower intrinsic gain and higher device mismatch. Thus, it has been difficult to design high-speed ADCs with low-power operation using traditional architectures without relying on increasingly complex digital calibration algorithms.
This research presents three ADCs that introduce novel architectures to relax the specifications of the analog circuits and reduce the complexity of the digital calibration algorithms. A low-pass sigma delta ADC with 15 MHz of bandwidth is introduced. The system uses a low-power 7-bit quantizer from which the four most significant bits are used for the operation of the sigma delta ADC. The remaining three least significant bits are used for the realization of a frequency domain algorithm for quantization noise improvement. The prototype was implemented in 130 nm CMOS technology. For this prototype, the use of the 7-bit quantizer and algorithm improved the SNDR from 69 dB to 75 dB. The obtained FoM was 145 fJ/conversion-step.
In a second project, the problem of high power consumption demanded from closed loop operational amplifiers operating at Giga hertz frequency is addressed. Especially the dependency of the power consumption to the closed loop gain. This project presents a low-pass sigma delta ADC with 75 MHz bandwidth. The traditional summing amplifier used for excess loop compensation delay is substituted by a summing amplifier with current buffer that decouples the power consumption dependency with the closed loop gain. The prototype was designed in 40 nm CMOS technology achieving 64.9 dB peak SNDR. The operating frequency was 3.2 GHz, the total power consumption was 22 mW and FoM of 106 fJ/conversion-step.
In a third project, the same approach of decoupling the power consumption requirements from the closed loop gain is applied to a pipelined ADC. The traditional capacitive multiplying DAC used in the residual amplifier is substituted by a current mode DAC and a transimpedance amplifier. The prototype was implemented in 40 nm CMOS technology achieving 58 dB peak SNDR and 76 dB SFDR with 200 MHz sampling frequency. The ADC consumes 8.4 mW with a FoM of 64 fJ/Conversion-step
Bandwidth enhancement to continuous-time input pipeline ADCs
This paper presents design analysis and insights for a new
continuous-time input pipeline (CTIP) analog-to-digital converter (ADC)
architecture that has enhanced bandwidth. An all-pass filter-based
analog delay in the signal path allows bandwidth extension to Nyquist
signal bandwidths. A resetting integrator gain stage provides a signal
path delay helping to increase the bandwidth while reducing the power
cost. The noise filtering property of the resetting integrator gain
stage preserves the medium resistive input benefit of CTIP ADCs. The
resetting integrator allows the architecture to be implemented with a
feedforward compensated op-amp using low-voltage CMOS processes. This
paper has been verified by simulation results of a CTIP ADC with 1.2-V
supply voltage designed in TSMC's 65-nm CMOS technology