Continuous-time analog two-dimensional IIR beam filters

Analog filter circuits that are realized in continuous-time discrete-space domain are proposed for implementing 2-D infinite impulse response (IIR) spatiotemporal transfer functions having beam-shaped passbands. These filters may be used for analog beamforming applications including seismic, audio, sonar, and ultrasonic signal processing. Unlike digital implementations, the proposed 2-D analog beam filters avoid the need for A/D conversions and digital circuitry. Importantly, the beam distortion (beam squint) due to bilinear transformation that is unavoidable in digital 2-D IIR beam filters is significantly reduced. A demonstrative example using operational amplifiers for first-order analog filters is provided

Digital and Mixed Domain Hardware Reduction Algorithms and Implementations for Massive MIMO

Emerging 5G and 6G based wireless communications systems largely rely on multiple-input-multiple-output (MIMO) systems to reduce inherently extensive path losses, facilitate high data rates, and high spatial diversity. Massive MIMO systems used in mmWave and sub-THz applications consists of hundreds perhaps thousands of antenna elements at base stations. Digital beamforming techniques provide the highest flexibility and better degrees of freedom for phased antenna arrays as compared to its analog and hybrid alternatives but has the highest hardware complexity. Conventional digital beamformers at the receiver require a dedicated analog to digital converter (ADC) for every antenna element, leading to ADCs for elements. The number of ADCs is the key deterministic factor for the power consumption of an antenna array system. The digital hardware consists of fast Fourier transform (FFT) cores with a multiplier complexity of (N log2N) for an element system to generate multiple beams. It is required to reduce the mixed and digital hardware complexities in MIMO systems to reduce the cost and the power consumption, while maintaining high performance. The well-known concept has been in use for ADCs to achieve reduced complexities. An extension of the architecture to multi-dimensional domain is explored in this dissertation to implement a single port ADC to replace ADCs in an element system, using the correlation of received signals in the spatial domain. This concept has applications in conventional uniform linear arrays (ULAs) as well as in focal plane array (FPA) receivers. Our analysis has shown that sparsity in the spatio-temporal frequency domain can be exploited to reduce the number of ADCs from N to where . By using the limited field of view of practical antennas, multiple sub-arrays are combined without interferences to achieve a factor of K increment in the information carrying capacity of the ADC systems. Applications of this concept include ULAs and rectangular array systems. Experimental verifications were done for a element, 1.8 - 2.1 GHz wideband array system to sample using ADCs. This dissertation proposes that frequency division multiplexing (FDM) receiver outputs at an intermediate frequency (IF) can pack multiple (M) narrowband channels with a guard band to avoid interferences. The combined output is then sampled using a single wideband ADC and baseband channels are retrieved in the digital domain. Measurement results were obtained by employing a element, 28 GHz antenna array system to combine channels together to achieve a 75% reduction of ADC requirement. Implementation of FFT cores in the digital domain is not always exact because of the finite precision. Therefore, this dissertation explores the possibility of approximating the discrete Fourier transform (DFT) matrix to achieve reduced hardware complexities at an allowable cost of accuracy. A point approximate DFT (ADFT) core was implemented on digital hardware using radix-32 to achieve savings in cost, size, weight and power (C-SWaP) and synthesized for ASIC at 45-nm technology

Continuous-time Algorithms and Analog Integrated Circuits for Solving Partial Differential Equations

Analog computing (AC) was the predominant form of computing up to the end of World War II. The invention of digital computers (DCs) followed by developments in transistors and thereafter integrated circuits (IC), has led to exponential growth in DCs over the last few decades, making ACs a largely forgotten concept. However, as described by the impending slow-down of Moore’s law, the performance of DCs is no longer improving exponentially, as DCs are approaching clock speed, power dissipation, and transistor density limits. This research explores the possibility of employing AC concepts, albeit using modern IC technologies at radio frequency (RF) bandwidths, to obtain additional performance from existing IC platforms. Combining analog circuits with modern digital processors to perform arithmetic operations would make the computation potentially faster and more energy-efficient. Two AC techniques are explored for computing the approximate solutions of linear and nonlinear partial differential equations (PDEs), and they were verified by designing ACs for solving Maxwell\u27s and wave equations. The designs were simulated in Cadence Spectre for different boundary conditions. The accuracies of the ACs were compared with finite-deference time-domain (FDTD) reference techniques. The objective of this dissertation is to design software-defined ACs with complementary digital logic to perform approximate computations at speeds that are several orders of magnitude greater than competing methods. ACs trade accuracy of the computation for reduced power and increased throughput. Recent examples of ACs are accurate but have less than 25 kHz of analog bandwidth (Fcompute) for continuous-time (CT) operations. In this dissertation, a special-purpose AC, which has Fcompute = 30 MHz (an equivalent update rate of 625 MHz) at a power consumption of 200 mW, is presented. The proposed AC employes 180 nm CMOS technology and evaluates the approximate CT solution of the 1-D wave equation in space and time. The AC is 100x, 26x, 2.8x faster when compared to the MATLAB- and C-based FDTD solvers running on a computer, and systolic digital implementation of FDTD on a Xilinx RF-SoC ZCU1275 at 900 mW (x15 improvement in power-normalized performance compared to RF-SoC), respectively

Low-Noise Amplifier and Noise/Distortion Shaping Beamformer

The emergence of advanced technologies has increased the need for fast and efficient mobile communication that can facilitate transferring large amounts of data and simultaneously serve multiple users. Future wireless systems will rely on millimeter-wave frequencies, enabled by recent silicon hardware advancements. High-frequency millimeter-wave technology and low-noise receiver front ends and amplifiers are key for improved performance and energy efficiency. This thesis proposes two LNA topologies that offer wide input-power-matched bandwidths and low noise figures, eliminating the need for complex matching networks at the LNA input. These topologies use intrinsic feedback through gate-drain networks and/or the resistance of the SOI-transistor back-gate terminal to achieve the real part of the input impedance. The two LNAs are experimentally demonstrated with two 22-nm FDSOI LNAs. One LNA, matched with the assistance of the gate-drain network, exhibits a bandwidth ranging from 7.7-33.3 GHz, which is further improved to 6-38.7 GHz through the application of the back-gate-resistance method. The two LNAs have noise-figure minima of 1.8 and 1.9 dB, maximum gains of 14.7 and 15.6 dB, and maximum IP1dBs of -9.1 and -7.8 dBm while consuming 10 and 7.8 mW of power and occupying 0.04 and 0.03 mm^2 of active areas, respectively. This thesis also presents the first experimental demonstration of noise/distortion (ND) shaping beamformer. The NDs originating in the receiver itself are spatio-temporally shaped away from the beamformer region of support, thereby permitting their suppression by the beamformer. The demonstrator is a 24.3-28.7 GHz, 79.28 mW 4-port receiver for a 4-element antenna array implemented in 22-nm FDSOI CMOS. When shaping was enabled, the concept demonstrator provided average improvements to the NF and IP1dB of 1.6 dB and 2.25 dB, respectively (compared to a reference design), and achieved NF=2.6 dB and IP1dB=-18.7dBm while consuming 19.8 mW/channel